i have a problem with my code it supposed to count from 0 to 99 but the problem that i have is that the counter starts at "80" and the Left number only increments at 10 seconds so it repeats..
Something like this
Starts at: 80 81 82 83 84 04 05 06 07 08 09
My code is this:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned;
-- pin 86 selector de display 1
-- pin 87 selec2 display
-- Seg A pin 85, Seg B 84, Seg C 83, D 82, E 81, F 78, Seg g pin 77, H 76
entity ContadorExamen is
port(
CLK : in std_logic; -- se le asigna el pin 12
--clk1hz : out std_logic ;-- se le asigna el pin 51
datos : out std_logic_vector (6 downto 0);
unidades : out std_logic;
decenas: out std_logic
);
end entity;
architecture BH_Examen2Parcial of ContadorExamen is
signal freq1 : integer range 0 to 5000 := 0;
signal freqDec : integer range 0 to 24999999 := 0;
signal freq100 : integer range 0 to 249999999 := 0;
signal tmp1 : std_logic := '0';
signal tmp100 : std_logic := '0';
signal tmpDec : std_logic := '0';
signal counterUnidades : integer range 0 to 10 := 0;
signal counterDecenas : integer range 0 to 10 := 0;
signal segDecenas : std_logic_vector(6 downto 0);
signal segUnidades : std_logic_vector(6 downto 0);
begin
process(CLK) is
begin
if(CLK'event and CLK = '1') then
if(freq1 >= 5000) then
freq1 <= 0;
tmp1 <= not tmp1;
else
freq1 <= freq1 + 1;
tmp1 <= tmp1;
end if;
if(freq100 >= 249999999) then
freq100 <= 0;
tmp100 <= not tmp100;
else
freq100 <= freq100 + 1;
tmp100 <= tmp100;
end if;
if(freqDec >= 24999999) then
freqDec <= 0;
tmpDec <= not tmpDec;
else
freqDec <= freqDec + 1;
tmpDec <= tmpDec;
end if;
end if;
end process;
-- principio de cambios en el programa
process(tmp1) is
begin
if(tmp1 = '1') then
unidades <= '0';
decenas <= '1';
datos <= segDecenas;
else
datos <= SegUnidades;
decenas <= '0';
unidades <= '1';
end if;
end process;
ParaContarUnidades:process(tmp100) is
begin
if (tmp100 = '1') then
if(counterUnidades = 0) then
segUnidades <= "0000001";
elsif (counterUnidades = 1 ) then
segUnidades <= "1001111";
elsif (counterUnidades = 2 ) then
segUnidades <= "0010010";
elsif (counterUnidades = 3 ) then
segUnidades <= "0000110";
elsif (counterUnidades = 4 ) then
segUnidades <= "1001100";
elsif (counterUnidades = 5 ) then
segUnidades <= "0100100";
elsif (counterUnidades = 6 ) then
segUnidades <= "1100000";
elsif (counterUnidades = 7 ) then
segUnidades <= "0001111";
elsif (counterUnidades = 8 ) then
segUnidades <= "0000000";
elsif (counterUnidades = 9) then
segUnidades <= "0001100";
else
segUnidades <= "1111111";
end if;
if(counterUnidades < 9) then
counterUnidades <= counterUnidades + 1;
else
counterUnidades <= 0;
end if;
end if;
end process;
ParaContarDecenas:process(tmpDec) is
begin
if (tmpDec = '1') then
if(counterDecenas = 0) then
segDecenas <= "0000001";
elsif (counterDecenas = 1 ) then
segDecenas <= "1001111";
elsif (counterDecenas = 2 ) then
segDecenas <= "0010010";
elsif (counterDecenas = 3 ) then
segDecenas <= "0000110";
elsif (counterDecenas = 4 ) then
segDecenas <= "1001100";
elsif (counterDecenas = 5 ) then
segDecenas <= "0100100";
elsif (counterDecenas = 6 ) then
segDecenas <= "1100000";
elsif (counterDecenas = 7 ) then
segDecenas <= "0001111";
elsif (counterDecenas = 8 ) then
segDecenas <= "0000000";
elsif (counterDecenas = 9) then
segDecenas <= "0001100";
else
segDecenas <= "1111111";
end if;
if(counterDecenas < 9) then
counterDecenas <= counterDecenas + 1;
else
counterDecenas <= 0;
end if;
end if;
end process;
end architecture;
A couple issues that you will want to look into:
Note that counterDecenas and counterUnidades should be in the sensitivity list of the processes that use them because (as written) you want your segUnidades and segDecenas signals to update when tmpDec or tmp100 remain '1' but the counters change.
Moreover, you assign the counters to values based on themselves (such as counterDecenas <= counterDecenas + 1;) outside of a clocked process - this will produce a combinatorial loop. These need to be triggered only on clock edges.
Beyond that, it isn't clear what this entity is supposed to do. You say it is supposed to count from 0 to 99, but this clearly does more than the 1-liner that it would take to implement what you've described the desired functionality to be.
Related
I'm building a "package sorter" which basically takes a weight, and adds it to a specific group based on that weight, and keeps track of how many weights (aka packages) are in each group using a simple counter. However, when running my test bench, I'm encountering weird red waves that shouldn't really be there:
Now I have read that these could mainly result from assigning the same signal a value from two different locations, however I've been failing to find the culprit and the deadline is nearing. Here is my code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity packageSorter is
port (clk,reset: in std_logic;
weight: in std_logic_vector (11 downto 0);
grp1: out std_logic_vector(7 downto 0);
grp2: out std_logic_vector(7 downto 0);
grp3: out std_logic_vector(7 downto 0);
grp4: out std_logic_vector(7 downto 0);
grp5: out std_logic_vector(7 downto 0);
grp6: out std_logic_vector(7 downto 0);
currentGrp: out std_logic_vector(2 downto 0)) ;
end packageSorter;
architecture beh of packageSorter is
signal count1 : integer range 0 to 256;
signal count2 : integer range 0 to 256;
signal count3 : integer range 0 to 256;
signal count4 : integer range 0 to 256;
signal count5 : integer range 0 to 256;
signal count6 : integer range 0 to 256;
signal lastWeight : std_logic_vector (11 downto 0);
signal currentWeight : std_logic_vector (11 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if(reset = '1') then
count1 <= 0;
count2 <= 0;
count3 <= 0;
count4 <= 0;
count5 <= 0;
count6 <= 0;
lastWeight <= "000000000000";
currentWeight <= Weight; -- intermediate signal equal to input
end if;
if to_integer(unsigned(lastWeight)) = 0 then --IF LAST WEIGHT WAS 0
if to_integer(unsigned(weight)) = 0 then
currentGrp <= std_logic_vector(to_unsigned(0,3));
elsif to_integer(unsigned(weight)) >= 1 and to_integer(unsigned(weight)) <= 200 then --group 1
count1 <= (count1 + 1);
currentGrp <= std_logic_vector(to_unsigned(1,3));
lastWeight <= weight;
elsif to_integer(unsigned(weight)) >= 201 and to_integer(unsigned(weight)) <= 500 then --group 2
count2 <= (count2 + 1);
currentGrp <= std_logic_vector(to_unsigned(2,3));
lastWeight <= weight;
elsif to_integer(unsigned(weight)) >= 501 and to_integer(unsigned(weight)) <= 800 then --group 3
count3 <= (count3 + 1);
currentGrp <= std_logic_vector(to_unsigned(3,3));
lastWeight <= weight;
elsif to_integer(unsigned(weight)) >= 801 and to_integer(unsigned(weight)) <= 1000 then --group 4
count4 <= (count4 + 1);
currentGrp <= std_logic_vector(to_unsigned(4,3));
lastWeight <= weight;
elsif to_integer(unsigned(weight)) >= 1001 and to_integer(unsigned(weight)) <= 2000 then --group 5
count5 <= (count5 + 1);
currentGrp <= std_logic_vector(to_unsigned(5,3));
lastWeight <= weight;
elsif to_integer(unsigned(weight)) >= 2000 then --group 6
count6 <= (count6 + 1);
currentGrp <= std_logic_vector(to_unsigned(6,3));
lastWeight <= weight;
end if;
elsif to_integer(unsigned(lastWeight)) /= 0 then
lastWeight <= std_logic_vector(unsigned(Weight) + unsigned(lastWeight));
currentWeight <= lastWeight; --currentWeight is whatever the input weight is
if to_integer(unsigned(currentWeight)) = 0 then
currentGrp <= std_logic_vector(to_unsigned(0,3));
lastWeight <= "000000000000";
elsif to_integer(unsigned(currentWeight)) >= 1 and to_integer(unsigned(currentWeight)) <= 200 then --group 1
currentGrp <= std_logic_vector(to_unsigned(1,3));
elsif to_integer(unsigned(currentWeight)) >= 201 and to_integer(unsigned(currentWeight)) <=500 then --group 2
currentGrp <= std_logic_vector(to_unsigned(2,3));
elsif to_integer(unsigned(currentWeight)) >= 501 and to_integer(unsigned(currentWeight)) <= 800 then --group 3
currentGrp <= std_logic_vector(to_unsigned(3,3));
elsif to_integer(unsigned(currentWeight)) >= 801 and to_integer(unsigned(currentWeight)) <= 1000 then --group 4
currentGrp <= std_logic_vector(to_unsigned(4,3));
elsif to_integer(unsigned(currentWeight)) >= 1001 and to_integer(unsigned(currentWeight)) <= 2000 then --group 5
currentGrp <= std_logic_vector(to_unsigned(5,3));
elsif to_integer(unsigned(currentWeight)) >= 2001 then --group 6
currentGrp <= std_logic_vector(to_unsigned(6,3));
end if;
end if;
end if;
end process;
grp1 <= std_logic_vector(to_unsigned(count1,8));
grp2 <= std_logic_vector(to_unsigned(count2,8));
grp3 <= std_logic_vector(to_unsigned(count3,8));
grp4 <= std_logic_vector(to_unsigned(count4,8));
grp5 <= std_logic_vector(to_unsigned(count5,8));
grp6 <= std_logic_vector(to_unsigned(count6,8));
end beh;
It is definitely worth noting that even the clock signal (Which triggers the counter on a rising edge) goes red and corrupt as shown in the first wave, despite not having any assignments to it. I have included my test bench as well as I'm not sure if the issue could be stemming from there but I doubt that is the case
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity packageSorter_TB is
end packageSorter_TB;
architecture tb of packageSorter_TB is
component packageSorter
port (clk,reset: in std_logic;
weight: in std_logic_vector (11 downto 0);
grp1: out std_logic_vector(7 downto 0);
grp2: out std_logic_vector(7 downto 0);
grp3: out std_logic_vector(7 downto 0);
grp4: out std_logic_vector(7 downto 0);
grp5: out std_logic_vector(7 downto 0);
grp6: out std_logic_vector(7 downto 0);
currentGrp: out std_logic_vector(2 downto 0));
end component;
signal TB_clk: std_logic := '0';
signal TB_reset : std_logic := '0';
signal TB_weight : std_logic_vector (11 downto 0) := "000000000000";
signal TB_grp1, TB_grp2, TB_grp3, TB_grp4, TB_grp5, TB_grp6 : std_logic_vector(7 downto 0) := "00000000";
signal TB_currentGrp: std_logic_vector(2 downto 0) := "000";
begin
UUT : packageSorter port map ( clk => TB_clk, reset => TB_reset, weight => TB_weight, grp1 => TB_grp1, grp2 => TB_grp2, grp3 => TB_grp3,
grp4 => TB_grp4, grp5 => TB_grp5, grp6 => TB_grp6, currentGrp => TB_currentGrp);
TB_clk <= '0' after 10 ns;
TB_clk <= '1' after 20 ns;
TB_weight <= "000011111010" after 30 ns; --250
TB_clk <= '0' after 40 ns, '1' after 50 ns;
TB_weight <= "000000000000" after 60 ns;
TB_clk <= '0' after 70 ns, '1' after 80 ns;
TB_weight <= "000111111010" after 90 ns; --506
-- TB_clk <= '0' after 35ns;
-- TB_clk <= '1' after 40ns;
-- TB_weight <= "000100000000" after 40ns;
-- TB_clk <= '0' after 45ns;
-- TB_clk <= '1' after 50ns;
-- TB_weight <= "000000000000" after 50ns;
-- TB_clk <= '0' after 55ns;
-- TB_clk <= '1' after 60ns;
-- TB_weight <= "000111110100" after 60ns;
-- TB_clk <= '0' after 65ns;
-- TB_reset <= '1' after 70ns;
-- TB_clk <= '1' after 75ns;
-- TB_weight <= "000000000001" after 75ns;
end tb;
I appreciate anybody that even read through these blocks of code. Thanks.
I'm trying to read input from the keypad and I want the number entered by the user to persist on a 7 segment display until another key is pressed.
Currently, the 7 segment display output disappears when the key is released. How can I make the 7 segment display output persist?
This is my entire code :
ARCHITECTURE Behavioral OF keypad IS
SIGNAL t1, t2, t3, t4: STD_LOGIC_VECTOR (1 TO 4) := "1111";
SIGNAL curr : STD_LOGIC_VECTOR(1 TO 4) := "0111";
BEGIN
proc_1: PROCESS
BEGIN
WAIT UNTIL rising_edge(clk);
IF curr <= "0111" THEN t1<= row ;
curr <= "1011";
ELSIF curr <= "1011" THEN t2<= row ;
curr <= "1101";
ELSIF curr <= "1101" THEN t3<= row ;
curr <= "1110";
ELSIF curr <= "1110" THEN t4<= row ;
curr <= "0111";
ELSE
curr <= "0111";
END IF ;
END PROCESS ;
proc_2: PROCESS (t1, t2, t3, t4)
BEGIN
hit <= '1';
IF t1(1) = '0' THEN sevenseg <= "1001111" ; --1
ELSIF t1(2) = '0' THEN sevenseg <= "1001100" ; --4
ELSIF t1(3) = '0' THEN sevenseg <= "0001111" ; --7
ELSIF t1(4) = '0' THEN sevenseg <= "1111111" ; --*
ELSIF t2(1) = '0' THEN sevenseg <= "0010010" ; --2
ELSIF t2(2) = '0' THEN sevenseg <="0100100" ; --5
ELSIF t2(3) = '0' THEN sevenseg <= "0000000" ; --8
ELSIF t2(4) = '0' THEN sevenseg <= "0000001" ; --0
ELSIF t3(1) = '0' THEN sevenseg <= "0000110" ; --3
ELSIF t3(2) = '0' THEN sevenseg <= "0100000" ; --6
ELSIF t3(3) = '0' THEN sevenseg <= "0000100" ; --9
ELSIF t3(4) = '0' THEN sevenseg <= "1111111" ; --#
ELSIF t4(1) = '0' THEN sevenseg <= "0001000" ; --A
ELSIF t4(2) = '0' THEN sevenseg <= "1111111" ; --B
ELSIF t4(3) = '0' THEN sevenseg <= "0110001" ; --C
ELSIF t4(4) = '0' THEN sevenseg <= "1111111" ; --D
ELSE
hit <= '0';
END IF;
END PROCESS;
col <= curr ;
END Behavioral ;
I'm trying to use a LCD project in my own project but I don't really
understand this project fully especially with the counters e.g count1 and count2
I can provide the datasheet if needed!
I hope I can get a clarification to this, I understand what is going on when counter has reached a certain number but what I do not understand is what is that number is representing!
I think something is worth mentioning is the clock used in the FPGA is 50MHz
the code is as fellow
library ieee;
use ieee.std_logic_1164.all;
entity display is
port( clk : in std_logic;
rst : in std_logic;
byte_ready : in std_logic;
RS : out std_logic;
RW : out std_logic;
E : out std_logic;
DB : out std_logic_vector(7 downto 0);
rxdata : in std_logic_vector(7 downto 0) );
end entity display;
architecture rtl of display is
signal cnt : integer range 0 to 1000000; -- init counter
signal cnt2 : integer range 0 to 50000000; -- counter that resets every time byte i recieved
begin
clk_gen : process(clk, cnt, rst)
begin
if (rst = '0') then
cnt <= 0;
cnt2 <= 0;
else
if rising_edge(clk) and cnt < 1000000 then
cnt <= cnt + 1;
elsif rising_edge(clk) and cnt = 1000000 then
if (byte_Ready = '1') then
cnt2 <= 0;
end if;
if (cnt2 < 5000000) then
cnt2 <= cnt2 + 1;
end if;
end if;
end if;
end process clk_gen;
p_main : process(clk, rst)
begin
if (rst = '1') then
if rising_edge(clk) then
case cnt is -- INIT
when 100000 =>
RS <= '0';
RW <= '0';
E <= '1';
DB <= "00111000"; -- function set --kan ändras till 00111011 western eurpean #2
when 140000 =>
E <= '0';
when 150000 =>
E <= '1';
DB <= "00001011"; -- display off
when 190000 =>
E <= '0';
when 200000 =>
E <= '1';
DB <= "00000001"; -- display clear
when 300000 =>
E <= '0';
when 350000 =>
E <= '1';
DB <= "00000110"; -- entry mode
when 390000 =>
E <= '0';
when 400000 =>
E <= '1';
DB <= "00000010"; -- home command
when 440000 =>
E <= '0';
when 450000 =>
E <= '1';
DB <= "00001111"; -- display on
when 490000 =>
E <= '0';
when 500000 =>
RS <= '0';
E <= '1';
DB <= "00010000"; -- cursor shift left
when 550000 =>
E <= '0';
when 600000 =>
RS <= '1';
E <= '1';
DB <= "10100000"; -- output space
when 650000 =>
E <= '0';
when 700000 =>
RS <= '0';
E <= '1';
DB <= "00010000"; -- cursor shift left
when 750000 =>
E <= '0';
when others => null;
end case;
if (rxdata = "01111111") then -- if input is backspace
case cnt2 is
when 300000 =>
RS <= '0';
E <= '1';
DB <= "00010000"; -- cursor shift left
when 350000 =>
E <= '0';
when 400000 =>
RS <= '1';
E <= '1';
DB <= "10100000"; -- output space
when 450000 =>
E <= '0';
when 500000 =>
RS <= '0';
E <= '1';
DB <= "00010000"; -- cursor shift left
when 550000 =>
E <= '0';
when others => null;
end case;
elsif (rxdata = "00001101") then -- if input is enter
case cnt2 is
when 300000 =>
RS <= '0';
E <= '1';
DB <= "11000000"; -- go to second row
when 350000 =>
E <= '0';
when others => null;
end case;
else
case cnt2 is
when 300000 =>
RS <= '1';
E <= '1';
DB <= rxdata; -- output character
when 350000 =>
E <= '0';
when others => null;
end case;
end if;
end if;
end if;
end process p_main;
end architecture rtl;
I am using a programmable-logic to decode a sequence of long or short impulses into latin letters according to morse code. I am using VHDL to describe our design, to be precise I'm using Quartus Prime for the design and ModelSim for the simulations. My CPLD is an ALTERA MAX-V 5M160ZE64C5.
Here is my code :
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all ;
use ieee.std_logic_arith.all;
entity SauvezLesMorses is
port
(
-- Input ports
clk : in std_logic;
message : in std_logic;
display : in std_logic;
start : in std_logic;
-- Output ports
seg14 : out std_logic_vector (13 downto 0);
lengthLED : out std_logic := '0'
);
end entity SauvezLesMorses;
architecture SauvezLesMorses_arch of SauvezLesMorses is
type state_t is (A, B, C);
signal state : state_t;
signal count : integer range 0 to 4 := 0;
signal clk_cnt : integer range 0 to 21 := 0;
signal morse : std_logic_vector (3 downto 0);
begin
process (clk, start)
variable vectorDummy : std_logic_vector (3 downto 0);
begin
if (start = '1') then
state <= A;
count <= 0;
seg14 <= "00000010001000";
morse <= "0000";
lengthLED <= '0';
elsif (rising_edge(clk)) then
case state is
-- Idle, listening
when A =>
if (display = '0') then
if (message = '1' and count < 4) then
state <= B;
seg14 <= "00000010001000";
count <= count;
morse <= morse;
lengthLED <= '0';
clk_cnt <= 0;
else
state <= A;
seg14 <= "00000010001000";
count <= count;
morse <= morse;
lengthLED <= '0';
end if;
else
state <= C;
count <= count;
morse <= morse;
lengthLED <= '0';
seg14 <= "00000010001000";
end if;
-- Measuring impulse length
when B =>
if (display = '0') then
if (message = '1') then
state <= B;
count <= count;
morse <= morse;
seg14 <= "00000010001000";
if (clk_cnt < 20) then
clk_cnt <= (1 + clk_cnt);
lengthLED <= '0';
else
clk_cnt <= 21;
lengthLED <= '1';
end if;
else
state <= A;
if (clk_cnt < 21) then
morse <= morse;
else
case count is
when 0 => vectorDummy := "1000";
when 1 => vectorDummy := "0100";
when 2 => vectorDummy := "0010";
when 3 => vectorDummy := "0001";
when others => vectorDummy := "0000";
end case;
morse <= morse or vectorDummy;
end if;
count <= count + 1;
lengthLED <= '0';
seg14 <= "00000010001000";
end if;
else
state <= C;
count <= count;
morse <= morse;
lengthLED <= '0';
seg14 <= "00000010001000";
end if;
-- Displaying converted character to user
when C =>
if (display = '0') then
state <= A;
count <= 0;
seg14 <= "00000010001000";
lengthLED <= '0';
morse <= "0000";
else
state <= C;
count <= count;
morse <= morse;
lengthLED <= '0';
if(count = 1) then
case morse is
when "0000" => seg14 <= "10011110001000"; --E
when "1000" => seg14 <= "10000000100010"; --T
when others => seg14 <= "11111111111111"; --unknown character
end case;
elsif(count = 2) then
case morse is
when "0100" => seg14 <= "11101110001000"; --A
when "1000" => seg14 <= "01101101000100"; --N
when "1100" => seg14 <= "01101101010000"; --M
when "0000" => seg14 <= "00000000100010"; --I
when others => seg14 <= "11111111111111"; --unknown character
end case;
elsif(count = 3) then
case morse is
when "0000" => seg14 <= "10110110001000"; --S
when "0010" => seg14 <= "01111100000000"; --U
when "0100" => seg14 <= "11001110001100"; --R
when "0110" => seg14 <= "01101100000101"; --W
when "1000" => seg14 <= "11110000100010"; --D
when "1010" => seg14 <= "00001110010100"; --K
when "1100" => seg14 <= "10111100001000"; --G
when "1110" => seg14 <= "11111100000000"; --O
when others => seg14 <= "11111111111111"; --unknown character
end case;
elsif(count = 4) then
case morse is
when "0000" => seg14 <= "01101110001000"; --H
when "0001" => seg14 <= "00001100010001"; --V
when "0010" => seg14 <= "10001110001000"; --F
when "0100" => seg14 <= "00011100000000"; --L
when "0110" => seg14 <= "11001110001000"; --P
when "0111" => seg14 <= "01111000000000"; --J
when "1000" => seg14 <= "11110000101010"; --B
when "1001" => seg14 <= "00000001010101"; --X
when "1010" => seg14 <= "10011100000000"; --C
when "1011" => seg14 <= "00000001010010"; --Y
when "1100" => seg14 <= "10010000010001"; --Z
when "1101" => seg14 <= "11111100000100"; --Q
when others => seg14 <= "11111111111111"; --unknown character
end case;
else
seg14 <= "11111111111111";
end if ;
end if;
end case;
end if;
end process;
end architecture SauvezLesMorses_arch ;
A modelsim simulation with parameters
force -freeze sim:/sauvezlesmorses/clk 1 0, 0 {25000000000 ps} -r {50 ms}
force -freeze sim:/sauvezlesmorses/display 0 0, 1 {9000000000000 ps} -r {18 sec}
force -freeze sim:/sauvezlesmorses/message 0 0, 1 {3200000000000 ps} -r {6.4 sec}
force -freeze sim:/sauvezlesmorses/start 1 0 -cancel {0.5 sec}
run 40 sec
which yields :
Modelsim Simulation
clearly shows that :
clk_cnt never increases but rather remains zero for 40 seconds
count is neither set to 0 by the activation of start nor from the desactivation of display (i.e. the transition of state from C to A).
Would you have any idea why?
P.S. I know that I am positively not running a proper testbench. So even if I should, please do not remind it to me unless you know it is part of the answer to my question.
A force updating a signal value doesn't generate an event.
See IEEE Std 1076-2008 14.7.3.4 Signal update, para 3
... If updating a signal causes the current value of that signal to change, then an event is said to have occurred on the signal, unless the update occurs by application of the vhpi_put_value function with an update mode of vhpiDeposit or vhpiForce to an object that represents the signal. ...
Likely the same mechanism used by Modelsim's force or FLI.
With a testbench:
library ieee;
use ieee.std_logic_1164.all;
entity slm_tb is
end entity;
architecture foo of slm_tb is
-- Input ports
signal clk: std_logic := '1';
signal message: std_logic := '0';
signal display: std_logic := '0';
signal start: std_logic := '1';
-- Output ports
signal seg14: std_logic_vector (13 downto 0);
signal lengthLED: std_logic;
begin
DUT:
entity work.sauvezlesmorses
port map (
clk => clk,
message => message,
display => display,
start => start,
seg14 => seg14,
lengthLED => lengthLED
);
-- force -freeze sim:/sauvezlesmorses/clk 1 0, 0 {25000000000 ps} -r {50 ms}
-- force -freeze sim:/sauvezlesmorses/display 0 0, 1 {9000000000000 ps} -r {18 sec}
-- force -freeze sim:/sauvezlesmorses/message 0 0, 1 {3200000000000 ps} -r {6.4 sec}
-- force -freeze sim:/sauvezlesmorses/start 1 0 -cancel {0.5 sec}
-- run 40 sec
-- stimulus generators:
CLOCK:
process
begin
wait for 25 ms;
clk <= not clk;
if now > 40 sec then
wait;
end if;
end process;
DISP:
process
begin
wait for 9 sec;
display <= not display;
if now > 35 sec then -- stop simulation at 40 sec
wait;
end if;
end process;
MSG:
process
begin
wait for 3.2 sec;
message <= not message;
if now > 35 sec then
wait;
end if;
end process;
ST:
process
begin
wait for 0.5 sec;
start <= 'U';
wait;
end process;
end architecture;
You do get events:
My code is about a ping pang game using VHDL and maxplus2. I can't get it complied.
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.std_logic_unsigned.all;
-- use ieee.std_logic_arith.all;
entity center is
port (
clk: in std_logic;
ca: in std_logic;
cb: in std_logic;
enable: in std_logic;
a: in std_logic;
b: in std_logic;
ball: out std_logic_vector(16 downto 0);
sa: out std_ulogic;
sb: out std_ulogic;
over: inout std_ulogic
);
end center;
architecture behavior of center is
signal direction : integer range 0 to 2;
signal num : integer range -1 to 17;
begin
process (enable,ca,cb,a,b,clk)
begin
if enable = '0' then
over <= '0';
sa <= '0';
sb <= '0';
elsif enable = '1' and rising_edge(clk) then
if direction = 2 then
if ca = '1' then
direction <= 0;
num <= 1;
elsif cb = '1' then
direction <= 1;
num <= 16;
else
direction <= 2;
num <= 8;
end if;
elsif direction = 0 and num > 0 then
if b = '1' then
if num < 2 then
num <= num - 1;
direction <= 1;
else
direction <= 2;
sa <= '1' after 10 ns;
sb <= '0' after 10 ns;
over <= not over after 10 ns;
end if;
end if;
elsif direction = 1 and num <= 16 then
if a = '1' then
if num >= 14 then
num <= num + 1;
direction <= 2;
else
direction <= 2;
sa <= '0' after 10 ns;
sb <= '1' after 10 ns;
over <= not over after 10 ns;
end if;
end if;
elsif direction = 0 and num = -1 then
num <= 8;
direction <= 2;
sa <= '0' after 10 ns;
sb <= '1' after 10 ns;
over <= not over after 10 ns;
elsif direction = 0 and num = -1 then
num <= 8;
direction <= 2;
sa <= '0' after 10 ns;
sb <= '1' after 10 ns;
over <= not over after 10 ns;
end if;
end if;
end process;
end architecture behavior;
But I get a error:
signal parameter in a subprogram is not supported
I am confused, I don't know why I get this error.
I think as David also said you need to provide more information.
What it looks like for me is that your are writing a test bench the above code cannot be synthesized correctly. ISE will tell you that your syntax is ok but the delays are ignored IE the after keyword. The after keyword is only used in simulation.
That said i would also clean up the code there are a lot of redundancies. FX
The last two elsif statements. only one is needed. and the sensitivity list. only clk and enable should be there.
I've tried to clean up your code:
process (enable,clk)
begin
if enable = '0' then
over <= '0';
sa <= '0';
sb <= '0';
elsif rising_edge(clk) then
case( direction ) is
when 0 =>
if num > 0 then
if b = '1' then
if num < 2 then
num <= num - 1;
direction <= 1;
else
direction <= 2;
sa <= '1' after 10 ns;
sb <= '0' after 10 ns;
over <= not over after 10 ns;
end if;
end if;
elsif num = -1 then
num <= 8;
direction <= 2;
sa <= '0' after 10 ns;
sb <= '1' after 10 ns;
over <= not over after 10 ns;
end if;
when 1 =>
if num <= 16 then
if a = '1' then
if num >= 14 then
num <= num + 1;
direction <= 2;
else
direction <= 2;
sa <= '0' after 10 ns;
sb <= '1' after 10 ns;
over <= not over after 10 ns;
end if;
end if;
end if;
when 2 =>
if ca = '1' then
direction <= 0;
num <= 1;
elsif cb = '1' then
direction <= 1;
num <= 16;
else
direction <= 2;
num <= 8;
end if;
when others => NULL;
end case ;
end if;
end process;
Try and remove your after keywords and see if it will compile then.