I am trying to make a generic 8 bit adder subtractor and I wrote all the code bit it gives me an syntax error on Line "big_mode <= (others => mode);".. any help?
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY AdderSubtractor IS
GENERIC(n: NATURAL :=8);
PORT ( Number1 : IN STD_LOGIC_VECTOR (n-1 DOWNTO 0);
Number2 : IN STD_LOGIC_VECTOR (n-1 DOWNTO 0);
Mode : IN STD_LOGIC;
Sum : OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0);
Carry : OUT STD_LOGIC);
END AdderSubtractor;
ARCHITECTURE Behavioral OF AdderSubtractor IS
SIGNAL Tmp: STD_LOGIC_VECTOR (n DOWNTO 0);
SIGNAL big_mode: STD_LOGIC_VECTOR (n DOWNTO 0);
BEGIN
zeros<=(others=>'0');
big_mode <= (others => mode);
tmp<=('0' & Number1 + (('0' & Number2) xor big_mode)+mode);
Sum <= Tmp(n-1 DOWNTO 0);
Carry <= Tmp(n);
END Behavioral;
zeros isn't declared in your example code. On the line before the one you claim has a syntax error (and doesn't apparently).
Commenting out
-- zeros<=(others=>'0');
And your code analyzes.
You likely can comment out:
-- use ieee.std_logic_arith.all;
You're not using any declarations from it (so far).
You could also be using package numeric_std_unsigned instead of the Synopsys packages.
What VHDL tool are you using? (You didn't show us the exact wording of your syntax error).
Related
I'm writing a simple program using Spartan 6 for signed numbers but this error pops up says :hdl 806"near line 12 syntax error"
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Multiplier_Top is
Port (
A : in signed (15 downto 0);
B : in signed (15 downto 0);
Sum : out signed (15 downto 0);
Overflow : out STD_LOGIC;
);
end Multiplier_Top;
architecture Behavioral of Multiplier_Top is
signal Sum_Int signed (16 downto 0) :=(others=>'0');
begin
Sum_Int <= Resize(A,17) + B;
Sum <= Sum_Int(15 downto 0);
Overflow <= Sum_Int(16) xor Sum_Int(15);
end Behavioral;
There are 2 syntax error in the design:
Line 11: Remove the ; after out STD_LOGIC; so it becomes out std_logic
Line 17: Insert a : in Sum_Int signed so it becomes Sum_Int : signed
Some other comments:
Line 17: Remove default value assign :=(others=>'0'), since that is not required when output is assigned by continuous assignment in line 21
Line 17 and others: Use VHDL attributes line 'length to avoid constants in code
The code can then look like this:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Multiplier_Top is
port (
A : in signed (15 downto 0);
B : in signed (15 downto 0);
Sum : out signed (15 downto 0);
Overflow : out std_logic
);
end Multiplier_Top;
architecture Behavioral of Multiplier_Top is
signal Sum_Int : signed (A'length downto 0); -- Length one bit more than A, assuming same length as B
begin
Sum_Int <= Resize(A, Sum_Int'length) + B;
Sum <= Sum_Int(Sum'range);
Overflow <= Sum_Int(Sum_Int'left) xor Sum_Int(Sum_Int'left - 1);
end Behavioral;
i am learning vhdl and i get an error when i simulate a 3-bit full adder
that implements with std_logic_vector (because of ability to use '+' operation)
just an example that our teacher gave us,
forgive me if it is a simple question...
here is code :
Library ieee;
use ieee.std_logic_1164.all;
entity adder_3_bit is
port(
a,b : in std_logic_vector(2 downto 0);
cin : in std_logic;
cout : out std_logic;
sum : out std_logic_vector(2 downto 0)
);
end adder_3_bit;
architecture behav of adder_3_bit is
signal temp : std_logic_vector(3 downto 0);
begin
temp <= ('0' & a) + ('0' & b) + ("000" & cin);
sum <= temp(2 downto 0);
cout <= temp(3);
end behav;
i get an error when temp is trying to add 0's at then end of 2 bit arrays,
which it says :
Line 15: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"ERROR:HDLCompiler:854
every body here is the working code:
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder_3_bit is
port (
a,b : in std_logic_vector(2 downto 0);
cin : in std_logic;
cout : out std_logic;
sum : out std_logic_vector(2 downto 0)
);
end adder_3_bit;
architecture behav of adder_3_bit is
signal temp : std_logic_vector(3 downto 0);
begin
temp <= std_logic_vector(('0' & unsigned (a)) + ('0' & unsigned(b)) + ("000" & cin));
sum <= temp(2 downto 0);
cout <= temp(3);
end behav;
Without any additional libraries, you cannot add signals of type std_logic_vector. There is no + operator defined that takes two std_logic_vector arguments. The correct way to do this is to include the numeric_std package and cast your arguments to unsigned for your additions.
use ieee.numeric_std.all;
temp <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b) + unsigned("000" & cin));
In practice, most people don't create a whole entity for such a simple operation so there are fewer casts as your signals are in the correct type for the data already (numbers use unsigned, collections of bits use std_logic_vector), which is why this looks a bit awkward.
You could also get by doing this with the synopsis package (std_logic_unsigned) and it would look a little cleaner (no casts), but that package is not part of the VHDL standard and its use has been deprecated.
I am trying to program an FPU unit in VHDL. I am doing my first steps. I get two errors while executing this instruction:
mantissa1 <= std_logic_vector(resize(unsigned(mantissa1),mantissa1'length + d));
The errors are:
Error: C:/Modeltech_pe_edu_10.4a/examples/fpu/shifter.vhd(38): Illegal type conversion to ieee.std_logic_1164.STD_LOGIC_VECTOR (operand type is not known).
Error: C:/Modeltech_pe_edu_10.4a/examples/fpu/shifter.vhd(36): (vcom-1078) Identifier "unsigned" is not directly visible.
Here is my code
library ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_misc.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
use ieee.numeric_std.all;
entity fpu is
port (
E1,E2 : IN std_logic_vector( 30 downto 23);
M1,M2 : IN std_logic_vector( 22 downto 0);
S1,S2 : IN std_logic_vector (31 downto 31);
op : IN std_logic_vector (1 downto 0);
SUM : OUT std_logic_vector (45 downto 0);
E : OUT std_logic_vector (7 downto 0);
clk : IN std_logic
);
end entity;
architecture arch_fpu of fpu is
SIGNAL d: integer;
SIGNAL mantissa1 : std_logic_vector (22 DOWNTO 0) ;
SIGNAL mantissa2 : std_logic_vector (22 DOWNTO 0) ;
begin
process(E1,E2,M1,M2,S1,S2,clk)
BEGIN
if((op="01") or (op="00")) then
E<=E1 when E1>E2 else
E2;
d<=abs(conv_integer(E1-E2));
mantissa1 <= std_logic_vector(resize(unsigned(mantissa1),mantissa1'length + d));
end if;
END process;
end arch_fpu;
You are mixing VHDL math libraries. I suggest you use either numeric_std (my preference) or std_logic_unsigned/std_logic_arith, but not both.
There are several other issues as well. You cannot assign the larger (by 'd' bits) manitissa1 value back to manitissa1, you need a target of the appropriate size. Your subtraction of E1-E2 will need some type conversion to be legal, perhaps: signed(E1) - signed(E2)
Honestly, you probably want to rethink the whole approach to what you are trying to do, especially if you expect to synthesize this code into logic.
I am trying to add two std_logic_vectors using the notation given below:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.NUMERIC_STD.ALL;
entity adder is
port( a:in std_logic_vector(31 downto 0);
b:in std_logic_vector(31 downto 0);
o:out std_logic_vector(31 downto 0));
end adder;
architecture Behavioral of adder is
begin
o<=a+b;
end Behavioral;
One possibility is to generate the result with carry, and then split that afterwards, like:
architecture Behavioral of adder is
signal c_o : std_logic_vector(o'length downto 0); -- Result with carry
signal c : std_logic; -- Carry only
begin
c_o <= ('0' & a) + b; -- Result with carry; extended with '0' to keep carry
o <= c_o(o'range); -- Result without carry
c <= c_o(c_o'left); -- Carry only
end Behavioral;
You can do this. The carry is not saved, but it's being reported that there was an overflow.
function "+" (Add1: std_logic_vector; Add2: std_logic_vector) return std_logic_vector is
variable big_sum: bit_vector(Add1'LENGTH downto 0);
begin
big_sum = Add1 + Add2;
assert big_sum(Add1'LENGTH) = 0
report "overflow"
severity warning;
return big_sum(Add1'LENGTH-1 downto 0);
Of course you'll need to define a new package and also include that package in your already existing file.
o<=std_logic_vector(unsigned(a)+unsigned(b))
Although I suggest you use unsigned/signed on your ports (and have a clock cycle of latency).
If you want the carry
o_with_carry <= std_logic_vector('0'&unsigned(a)+unsigned(b));
o_carry <= o_with_carry(o_with_carry'high);
o <= o_with_carry(o'range);
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity leftshift is
Port ( Din : in STD_LOGIC_VECTOR (31 downto 0);
Dout : out STD_LOGIC_VECTOR (31 downto 0));
end leftshift;
architecture Behavioral of leftshift is
signal t1: std_logic_vector (33 downto 0);
begin
t1 <= Din sll 2;
Dout <= t1(33 downto 2)
end Behavioral;
This is my code, but I don't know why I'm getting the error.
found '0' definitions of operator "sll", cannot determine exact overloaded matching definition for "sll"
I also tried using just Dout <= Din sll 2 but it still doesn't work. Please help me.
another way to shift left (on a 16-bit word for example):
VECT <= VECT(14 DOWNTO 0) & '0';
As rick pointed out in his answer, you can't do sll on a std_logic_vector until VHDL 2008, which is not (and sadly, may never be) well supported in many existing modern FPGA and ASIC toolchains.
One easy workaround is to convert to the standard unsigned type from ieee.numeric_std, do the shift, then convert back to std_logic_vector
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- use IEEE.STD_LOGIC_UNSIGNED.ALL; -- remove this non-standard package
...
t1 <= std_logic_vector(unsigned(Din) sll 2);
The shift operators (sll included) are defined for std_logic_vectors in VHDL 2008. If you want to use them, just tell your compiler that you are working with this version of VHDL.
Apart from that, there is one mistake in your code: you are trying to assign a 32-bit value to a 34-bit signal (on line t1 <= Din sll 2;). This can be fixed by changing the offending line to t1 <= (Din sll 2) & "00";
Other than that, there is nothing wrong with your code. I ran it through Modelsim Altera SE 10.1b and it compiles and works correctly. Can you tell us what tool version are you using?
Finally, here is a cleaner version of your code, without any auxiliary signals.
library ieee;
use ieee.std_logic_1164.all;
entity shift_left_by_two is
port (
Din: in std_logic_vector(31 downto 0);
Dout: out std_logic_vector(31 downto 0)
);
end;
architecture behavioral of shift_left_by_two is
begin
Dout <= Din sll 2;
end behavioral;
Or use:
Dout <= Din((31-2) downto 0) & Din(31 downto (31-2));
Same as sll 2;
My version does not recognize all sll 2, however.
Lets use a fixed size as it will be easier to follow:
signal a, b : std_logic_vector(7 downto 0);
Shift operators:
b <= a sll 2' eq 'b <= a(5 downto 0) & "00"
b <= a srl 2' eq 'b <= "00" & a(7 downto 2)
sal and sar will care about the sign bit.
Roll Opperators:
b <= a rol 2' eq 'b <= a(5 downto 0) & a(7 downto 6)
b <= a ror 2' eq 'b <= a(1 downto 0) & a(7 downto 6)
http://vhdl.renerta.com/mobile/source/vhd00047.htm