full adder 3-bit std_logic_vector - vhdl

Question

i am learning vhdl and i get an error when i simulate a 3-bit full adder
that implements with std_logic_vector (because of ability to use '+' operation)
just an example that our teacher gave us,
forgive me if it is a simple question...
here is code :
Library ieee;
use ieee.std_logic_1164.all;
entity adder_3_bit is
port(
a,b : in std_logic_vector(2 downto 0);
cin : in std_logic;
cout : out std_logic;
sum : out std_logic_vector(2 downto 0)
);
end adder_3_bit;
architecture behav of adder_3_bit is
signal temp : std_logic_vector(3 downto 0);
begin
temp <= ('0' & a) + ('0' & b) + ("000" & cin);
sum <= temp(2 downto 0);
cout <= temp(3);
end behav;
i get an error when temp is trying to add 0's at then end of 2 bit arrays,
which it says :
Line 15: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"ERROR:HDLCompiler:854
every body here is the working code:
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder_3_bit is
port (
a,b : in std_logic_vector(2 downto 0);
cin : in std_logic;
cout : out std_logic;
sum : out std_logic_vector(2 downto 0)
);
end adder_3_bit;
architecture behav of adder_3_bit is
signal temp : std_logic_vector(3 downto 0);
begin
temp <= std_logic_vector(('0' & unsigned (a)) + ('0' & unsigned(b)) + ("000" & cin));
sum <= temp(2 downto 0);
cout <= temp(3);
end behav;

Answer 1

Without any additional libraries, you cannot add signals of type std_logic_vector. There is no + operator defined that takes two std_logic_vector arguments. The correct way to do this is to include the numeric_std package and cast your arguments to unsigned for your additions.
use ieee.numeric_std.all;
temp <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b) + unsigned("000" & cin));
In practice, most people don't create a whole entity for such a simple operation so there are fewer casts as your signals are in the correct type for the data already (numbers use unsigned, collections of bits use std_logic_vector), which is why this looks a bit awkward.
You could also get by doing this with the synopsis package (std_logic_unsigned) and it would look a little cleaner (no casts), but that package is not part of the VHDL standard and its use has been deprecated.