Square Waveform Generation in VHDL - vhdl

Question

I'm working on a stopwatch project in VHDL but I don't know how to make the CLK square waveform of the counter? Please help.
Here is my code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity Circuit is
Port ( CLK : in STD_LOGIC := '0';
CLR : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (5 downto 0));
end Circuit;
architecture Behavioral of Circuit is
signal s: STD_LOGIC_VECTOR := "000000";
begin
process (CLK, CLR)
begin
if rising_edge(CLK) then
if CLR = '1' OR s = "111011" then
s <= "000000";
else
s <= s+1;
end if;
end if;
end process;
Q <= s;
end Behavioral;

Answer 1

Let's say your clock is 1 MHz, but you want the seconds counter process to work at 1 Hz. You would need to divide the incoming clock by 1 million.
constant CLOCK_DIVIDER : integer := 1000000;
signal clock_divide_counter : integer range 0 to CLOCK_DIVIDER-1 := 0;
signal one_hz_pulse : std_logic := '0';
...
process (clk)
begin
if (rising_edge(clk)) then
if (clock_divide_counter = CLOCK_DIVIDER - 1) then
clock_divide_counter <= 0;
one_hz_pulse <= '1';
else
clock_divide_counter <= clock_divide_counter + 1;
one_hz_pulse <= '0';
end if;
end if;
end process;
then modify your existing process to only be enabled when the 1 Hz pulse is high:
process (CLK, CLR)
begin
if rising_edge(CLK) then
if (CLR = '1') then
s <= "000000";
elsif (one_hz_pulse = '1') then
if s = "111011" then
s <= "000000";
else
s <= s+1;
end if;
end if;
end if;
end process;
I haven't run the code, but you should get the idea.