Servo Control using FPGA (Altera DE2) - vhdl

Question

I am creating a VHDL code for controlling servo position using 8 switches on DE2 development kit. When the code is done, I tested the code with the servo motor but it is not working. Then I did a waveform simulation with timing analysis, I found that there is some glitches in the wave. Is it glitch the reason why this is not working? If yes, how can I solve this?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity servo_pwm is
PORT (
clk50 : IN STD_LOGIC;
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
position : IN STD_LOGIC_VECTOR(7 downto 0);
servo : OUT STD_LOGIC
);
end servo_pwm;
architecture Behavioral of servo_pwm is
signal cnt : unsigned(11 downto 0);
signal pwmi: unsigned(7 downto 0);
begin
pwmi <= unsigned(position);
start: process (reset, clk) begin
if (reset = '1') then
cnt <= (others => '0');
elsif rising_edge(clk) then
if (cnt = 2559) then
cnt <= (others => '0');
else
cnt <= cnt + 1;
end if;
end if;
end process;
servo <= '1' when (cnt < pwmi) else '0';
end Behavioral;
Clock divider:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk64kHz is
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
clk_out: out STD_LOGIC
);
end clk64kHz;
architecture Behavioral of clk64kHz is
signal temporal: STD_LOGIC;
signal counter : integer range 0 to 195 := 0; --position 8bit
begin
freq_divider: process (reset, clk) begin
if (reset = '1') then
temporal <= '0';
counter <= 0;
--elsif rising_edge(clk) then
elsif (clk'event and clk = '1') then
--if (counter = 390) then
if (counter = 195) then
temporal <= NOT(temporal);
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
clk_out <= temporal;
end Behavioral;
Vector waveform file: