VHDL delayed monostable initialisation - vhdl

Question

Idea is to generate a delayed pulse when Trig input is activated, both delay and pulse width are adjustable respectively with 'delay' and 'ton'. I use an integer counter to compare delay then delay+ton to toggle the Pulse output.
The issue is that timing sequence starts just after board programming: sigPulseCounter is incremented ... even if signals are initialized. Any tips ?
Reset works well and Trig also but there is an unwanted pulse on startup.
Thanks for your feedback.
library ieee;
use ieee.std_logic_1164.all;
entity DelayedMonostable is
generic(
delay :integer:= 2*40000000;
ton :integer:= 2*40000000);
port (
Clk: in std_logic;
Reset: in std_logic;
Trig: in std_logic;
Pulse: out std_logic;
Debug: out std_logic);
end DelayedMonostable;
architecture Behavioral of DelayedMonostable is
-- Signal declaration
signal sigPulseCounterEnable: std_logic := '0';
signal sigPulseCounter : integer := 0;
signal sigPulse : std_logic :='0';
signal sigDebug: std_logic := '0';
begin
Debug <= not sigPulseCounterEnable;
Pulse <= not sigPulse;
Counter : process(Clk, Reset)
begin
if Reset='0' then
sigPulseCounter <= 0;
sigPulseCounterEnable <= '0';
sigPulse <= '0';
elsif Trig='0' then
sigPulseCounter <= 0;
sigPulseCounterEnable <= '1';
sigPulse <= '0';
elsif rising_edge(Clk) then
if(sigPulseCounterEnable='1') then
if(sigPulseCounter = delay) then
sigPulse <= '1';
end if;
if(sigPulseCounter = delay+ton) then
sigPulse <= '0';
sigPulseCounterEnable <= '0';
sigPulseCounter <= 0;
end if;
sigPulseCounter <= sigPulseCounter + 1;
end if;
end if;
end process Counter;
end Behavioral;
I have tried to invert the Trig logic in the process without success:
elsif Trig='0'
with
elsif Trig='1'
EDIT:
I have split in 3 parts the architecture, each assign value to a signal or port - Works good now.
library ieee;
use ieee.std_logic_1164.all;
entity DelayedMonostable is
generic(
delay : integer := 40000000/2;
ton : integer := 2*40000000);
port(
Clk: in std_logic;
Reset: in std_logic;
Trig: in std_logic;
Pulse: out std_logic;
Debug: out std_logic);
end DelayedMonostable;
---------------------------------------
architecture Behavioral of DelayedMonostable is
-- Signal declaration
signal PWMCounter : integer;
signal sigTrig: std_logic;
begin
Debug <= not sigTrig;
Counter : process(Clk, Reset)
begin
if (Reset='0') then
PWMCounter <= 0;
elsif(rising_edge(Clk) and sigTrig='1') then
if(PWMCounter = ton+delay) then
PWMCounter <= 0;
else
PWMCounter <= PWMCounter + 1;
end if;
end if;
end process Counter;
Trigger: process(Reset, Trig)
begin
if (Reset='0') then
sigTrig <= '0';
elsif (Trig='0') then
sigTrig <= '1';
elsif (PwmCounter = ton+delay) then
sigTrig <= '0';
end if;
end process Trigger;
Generator : process(Clk, Reset)
begin
if (Reset='0') then
Pulse <= not '0';
elsif(rising_edge(Clk)) then
if(PwmCounter=delay) then
Pulse <= not '1';
end if;
if(PwmCounter=delay+ton) then
Pulse <= not '0';
end if;
end if;
end process Generator;
end Behavioral;