I wrote the code for 8 bit adder by usign 4 bit carry look ahead adder. i instantiated the 4 bit caryy look ahed adder using port map. but i think i am wrong for port mapping . plese any one can hel me , how can i correct the port mapping ..
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity adder_4_bit is
Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0);
s : out STD_LOGIC_VECTOR (3 downto 0);
cout: out STD_LOGIC);
end adder_4_bit;
architecture Behavioral of adder_4_bit is
signal g, p, c, b1: STD_LOGIC_VECTOR(3 downto 0);
begin
g <= a and b;
p <= a xor b;
s(0) <= p(0) ;
c(0) <= g(0) or p(0) ;
s(1) <= p(1) xor c(0);
c(1) <= g(1) or (p(1) and g(0)) or (p(1) and p(0));
s(2) <= p(2) xor c(1);
c(2) <= g(2) or (p(2) and g(1)) or (p(2) and p(1) and g(0)) or (p(2) and p(1) and p(0));
s(3) <= p(3) xor c(2);
c(3) <= g(3) or (p(3) and g(2)) or (p(3) and p(2) and g(1)) or (p(3) and p(2) and p(1) and g(0)) or (p(3) and p(2) and p(1) and p(0));
cout <= c(3);
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--********************************************************--
entity Adder_8_bit is
Port (
a,b : in STD_LOGIC_VECTOR (7 downto 0);
s : out STD_LOGIC_VECTOR (7 downto 0);
cout: out STD_LOGIC
);
end Adder_8_bit;k
---******************---
architecture Behavioral of Adder_8_bit is
component adder_4_bit is
Port (
A,B : in STD_LOGIC_VECTOR (3 downto 0);
S: out STD_LOGIC_VECTOR (3 downto 0);
cout: out STD_LOGIC
);
end component;
----
signal a1 ,b1 : STD_LOGIC_VECTOR (7 downto 0);
signal SUM : STD_LOGIC_VECTOR (7 downto 0);
begin
four_bit_adder1: adder_4_bit port map ( a1(3 downto 0) ,b1(3 downto 0) , SUM (3 downto 0) , cout) ;
four_bit_adder2: adder_4_bit port map ( a1(7 downto 4) ,b1(7 downto 4) , SUM (7 downto 4) , cout ) ;
end Behavioral;
You connect the signal cout to two drivers:
four_bit_adder1: adder_4_bit port map ( a1(3 downto 0) ,b1(3 downto 0) , SUM (3 downto 0) , cout);
four_bit_adder2: adder_4_bit port map ( a1(7 downto 4) ,b1(7 downto 4) , SUM (7 downto 4) , cout );
This is wrong, as the toplevel cout should have only 1 source, in this case the four_bit_adder2.
Your 4 bits adder also requires a carry in, otherwise it is impossible to chain two of them to form a 8 bits adder. The first adder's carry in is '0', the second adder's carry in is the first adder's carry out.
Related
i am a bit new to VHDL and i try to learn by examples. So long story short i began with some basic examples like creating this Full Adder.
entity FA is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end FA;
architecture gate_level of FA is
begin
S <= A XOR B XOR Cin ;
Cout <= (A AND B) OR (Cin AND A) OR (Cin AND B) ;
end gate_level;
After that i tried to implement this 4-bit adder
And this is the code that i wrote.
entity Ripple_Adder is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end Ripple_Adder;
architecture Behavioral of Ripple_Adder is
-- Full Adder VHDL Code Component Decalaration
component FA
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end component;
-- Intermediate Carry declaration
signal c1,c2,c3: STD_LOGIC;
begin
-- Port Mapping Full Adder 4 times
FA1: FA port map( A(0), B(0), Cin, S(0), c1);
FA2: FA port map( A(1), B(1), c1, S(1), c2);
FA3: FA port map( A(2), B(2), c2, S(2), c3);
FA4: FA port map( A(3), B(3), c3, S(3), Cout);
end Behavioral;
Also i used a 4_bit_adder test bench file and i found out that the output is right. Now i am trying to implement a 4 bit multiplier with the usage of the 4 bit adder but i am a bit stuck. Actually this is the multiplier that i am trying to implement.
the code i wrote is this, but i am stuck at the port map
--library
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_unsigned.all;
--entity
entity multy is
port (x: in std_logic_vector(3 downto 0);
y: in std_logic_vector(3 downto 0);
p : out std_logic_vector(7 downto 0)
);
end multy ;
-- architecture
architecture rtl of multy is
component Ripple_Adder
Port ( A : in std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
Cin : in std_logic;
S : out std_logic_vector (3 downto 0);
Cout : out std_logic);
end component ;
signal andgate: std_logic_vector(15 downto 0);
signal sumout: std_logic_vector( 11 downto 0);
signal carry: std_logic_vector(11 downto 0);
begin
andgate(0) <= x(0) and y(0);
andgate(1) <= x(1) and y(0); --b0
andgate(2) <= x(2) and y(0); --b1
andgate(3) <= x(3) and y(0); --b2
B
andgate(4) <= x(0) and y(1);
andgate(5) <= x(1) and y(1);
andgate(6) <= x(2) and y(1);
andgate(7) <= x(3) and y(1);
andgate(8) <= x(0) and y(2);
andgate(9) <= x(1) and y(2);
andgate(10) <= x(2) and y(2);
andgate(11) <= x(3) and y(2);
andgate(12) <= x(0) and y(3);
andgate(13) <= x(1) and y(3);
andgate(14) <= x(2) and y(3);
andgate(15) <= x(3) and y(3);
--gates
cell_1: Ripple_Adder port map();
cell_2: Ripple_Adder port map();
cell_3: Ripple_Adder port map();
--Assigning p values
p(0) <= andgate(0);
p(1) <= sumout(0);
p(2) <= sumout(4);
p(3) <= sumout(8);
p(4) <= sumout(9);
p(5) <= sumout(10);
p(6) <= sumout(11);
p(7) <= carry(11);
end rtl ;
"I am stuck on the port map" isn't a specific problem statement.
With named association members of formal ports in maps could be associated individually as well as in whole as long as all members of the formal are associated - IEEE Std 1076-2008 6.5.7 Association lists:
A formal interface object shall be either an explicitly declared interface object or member (see 5.1) of such an interface object. In the former case, such a formal is said to be associated in whole. In the latter cases, named association shall be used to associate the formal and actual; the subelements of such a formal are said to be associated individually. Furthermore, every scalar subelement of the explicitly declared interface object shall be associated exactly once with an actual (or subelement thereof) in the same association list, and all such associations shall appear in a contiguous sequence within that association list. Each association element that associates a slice or subelement (or slice thereof) of an interface object shall identify the formal with a locally static name.
Note you have too many carry elements (only need two), don't need andgate(0), don't need sumout(0), sumout(4) or sumout(11 downo 8), there's an extraneous character in the multy architecture, you're missing context clauses and have unused use clauses.
Your code using array intermediary signals:
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.std_logic_textio.all; -- NOT USED
-- use ieee.std_logic_unsigned.all; -- NOT USED
entity multy is
port (
x: in std_logic_vector (3 downto 0);
y: in std_logic_vector (3 downto 0);
p: out std_logic_vector (7 downto 0)
);
end entity multy;
architecture rtl of multy is
component Ripple_Adder
port (
A: in std_logic_vector (3 downto 0);
B: in std_logic_vector (3 downto 0);
Cin: in std_logic;
S: out std_logic_vector (3 downto 0);
Cout: out std_logic
);
end component;
-- AND Product terms:
signal G0, G1, G2: std_logic_vector (3 downto 0);
-- B Inputs (B0 has three bits of AND product)
signal B0, B1, B2: std_logic_vector (3 downto 0);
begin
-- y(1) thru y (3) AND products, assigned aggregates:
G0 <= (x(3) and y(1), x(2) and y(1), x(1) and y(1), x(0) and y(1));
G1 <= (x(3) and y(2), x(2) and y(2), x(1) and y(2), x(0) and y(2));
G2 <= (x(3) and y(3), x(2) and y(3), x(1) and y(3), x(0) and y(3));
-- y(0) AND products (and y0(3) '0'):
B0 <= ('0', x(3) and y(0), x(2) and y(0), x(1) and y(0));
-- named association:
cell_1:
Ripple_Adder
port map (
a => G0,
b => B0,
cin => '0',
cout => B1(3), -- named association can be in any order
S(3) => B1(2), -- individual elements of S, all are associated
S(2) => B1(1), -- all formal members must be provide contiguously
S(1) => B1(0),
S(0) => p(1)
);
cell_2:
Ripple_Adder
port map (
a => G1,
b => B1,
cin => '0',
cout => B2(3),
S(3) => B2(2),
S(2) => B2(1),
S(1) => B2(0),
S(0) => p(2)
);
cell_3:
Ripple_Adder
port map (
a => G2,
b => B2,
cin => '0',
cout => p(7),
S => p(6 downto 3) -- matching elements for formal
);
p(0) <= x(0) and y(0);
end architecture rtl;
And a borrowed testbench to demonstrate:
library ieee;
use ieee.std_logic_1164.all;
entity multy_tb is -- testbench
end entity;
architecture foo of multy_tb is
signal x, y: std_logic_vector (3 downto 0);
signal yp, rp: std_logic_vector (7 downto 0);
use ieee.numeric_std.all;
function to_string (inp: std_logic_vector) return string is
variable image_str: string (1 to inp'length);
alias input_str: std_logic_vector (1 to inp'length) is inp;
begin
for i in input_str'range loop
image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
end loop;
return image_str;
end function;
begin
DUT:
entity work.multy
port map (
x => x,
y => y,
p => yp
);
STIMULI:
process
begin
for i in 0 to 15 loop
x <= std_logic_vector(to_unsigned(i, x'length));
for j in 0 to 15 loop
y <= std_logic_vector(to_unsigned(j, y'length));
wait for 0 ns; -- assignments take effect
rp <= std_logic_vector(unsigned (x) * unsigned(y));
wait for 10 ns;
if yp /= rp then
report "multy error";
report HT & "expected " & to_string (rp);
report HT & "got " & to_string (yp);
end if;
end loop;
end loop;
wait;
end process;
end architecture;
The to_string function is included for pre -2008 simulators. Context clauses were added to FA and Ripple_Adder.
I am writing a code for 4*4 multiplier. Although, i am getting correct values for few inputs, it gives me wrong values for few other. Please suggest me what logical errors are present here as i am unable to spot them
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity multiplier is
Port ( a : in std_logic_vector (3 downto 0);
b : in std_logic_vector (3 downto 0);
result : out std_logic_vector (7 downto 0));
end multiplier;
architecture Behavioral of multiplier is
signal P0: std_logic_vector(7 downto 0);
signal P1: std_logic_vector(7 downto 0);
signal SP1: std_logic_vector(7 downto 0);
signal P2: std_logic_vector(7 downto 0);
signal SP2: std_logic_vector(7 downto 0);
signal P3: std_logic_vector(7 downto 0);
component genericadder
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
sum : out std_logic_vector (4 downto 0));
end component;
begin
result(0) <= a(0) and b(0);
P0(0) <= a(0) and b(1);
P0(1) <= a(0) and b(2);
P0(2) <= a(0) and b(3);
P0(3) <='0';
P0(4) <= a(1) and b(0);
P0(5) <= a(1) and b(1);
P0(6) <= a(1) and b(2);
P0(7) <= a(1) and b(3);
ga_for : genericadder
port map(
a =>P0( 3 downto 0),
b =>P0( 7 downto 4),
sum =>P1(4 downto 0));
result(1)<= P1(0);
SP1<= std_logic_vector(shift_right(unsigned(P1),1));
P1(4) <= a(2) and b(0);
P1(5) <= a(2) and b(1);
P1(6) <= a(2) and b(2);
P1(7) <= a(2) and b(3);
ga_for1 : genericadder
port map(
a =>SP1( 3 downto 0),
b =>P1( 7 downto 4),
sum =>P2(4 downto 0));
result(2) <= P2(0);
SP2<= std_logic_vector(shift_right(unsigned(P2),1));
P2(4) <= a(3) and b(0);
P2(5) <= a(3) and b(1);
P2(6) <= a(3) and b(2);
P2(7) <= a(3) and b(3);
ga_for2 : genericadder
port map(
a =>SP2( 3 downto 0),
b =>P2( 7 downto 4),
sum =>P3(4 downto 0));
result(3)<=P3(0);
result(4)<=P3(1);
result(5)<=P3(2);
result(6)<=P3(3);
result(7)<=P3(4);
end Behavioral;
entity genericadder is
generic (
n : Integer:=4
);
Port ( a : in STD_LOGIC_VECTOR (n-1 downto 0);
b : in STD_LOGIC_VECTOR (n-1 downto 0);
sum : out STD_LOGIC_VECTOR (n downto 0));
end genericadder;
--
The genericadder is made up of full adders. Please let me know the error. I am really unable to move ahead
7.1 - Consider an Arithmetic Circuit that can perform four operations: a+b, a-b, a+1 and a-1, where a and b are 16-bit Unsigned Numbers and the desired operation is specified by a 2-bit Control Signal, ctrl.
Is it possible to design this circuit just with one adder without using sequential logic.
I designed this circuit with 2's complementary logic but i cannot add logic (a + (not b) + 1) just one adder without memory components
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Ex_7_1_b is
generic( BUS_WIDTH : integer := 16 );
port ( a : in STD_LOGIC_VECTOR (BUS_WIDTH - 1 downto 0);
b : in STD_LOGIC_VECTOR (BUS_WIDTH - 1 downto 0);
ctrl : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC_VECTOR (BUS_WIDTH - 1 downto 0)
);
end Ex_7_1_b;
architecture Behavioral of Ex_7_1_b is
signal adder : unsigned(BUS_WIDTH - 1 downto 0);
signal mux_sign : unsigned(BUS_WIDTH - 1 downto 0);
signal mux_inp_sel : unsigned(BUS_WIDTH - 1 downto 0);
signal mux_val : unsigned(BUS_WIDTH - 1 downto 0);
signal result : unsigned(BUS_WIDTH - 1 downto 0);
begin
mux_val <= to_unsigned(0, mux_val'length) when ctrl(1) = '1' else to_unsigned(1, mux_val'length);
mux_inp_sel <= mux_val when ctrl(0) = '1' else unsigned(b);
mux_sign <= not (mux_inp_sel) when ctrl(1) = '1' else mux_inp_sel;
result <= unsigned(a) + mux_sign;
y <= std_logic_vector(result);
end Behavioral;
I designed this circuit with Renaud Pacalet contribute.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Ex_7_1_b is
generic( g_BUS_WIDTH : integer := 16 );
port (
i_a : in std_logic_vector (g_BUS_WIDTH - 1 downto 0);
i_b : in std_logic_vector (g_BUS_WIDTH - 1 downto 0);
i_ctrl : in std_logic_vector (1 downto 0);
o_y : out std_logic_vector (g_BUS_WIDTH - 1 downto 0)
);
end Ex_7_1_b;
architecture RTL of Ex_7_1_b is
signal r_A_Ext, r_B_Ext : unsigned(g_BUS_WIDTH downto 0);
signal r_Carry_In : std_logic;
signal r_Adder : unsigned(g_BUS_WIDTH - 1 downto 0);
signal w_Mux_Inv : unsigned(g_BUS_WIDTH - 1 downto 0);
signal w_Mux_Sel : unsigned(g_BUS_WIDTH - 1 downto 0);
signal r_Result : unsigned(g_BUS_WIDTH downto 0);
begin
r_A_Ext <= unsigned(i_a & '1');
w_Mux_Sel <= to_unsigned(1, w_Mux_Sel'length) when i_ctrl(1) = '1' else unsigned(i_b);
w_Mux_Inv <= not (w_Mux_Sel) when i_ctrl(0) = '1' else w_Mux_Sel;
r_Carry_In <= '1' when i_ctrl(0) = '1' else '0';
r_B_Ext <= w_Mux_Inv & r_Carry_In;
r_Result <= r_A_Ext + r_B_Ext;
o_y <= std_logic_vector(r_Result(g_BUS_WIDTH downto 1));
end RTL;
The solution you found yourself is fine but it uses a 17-bits adder instead of a 16-bits one. With smart enough synthesizers it should not make any difference. Just for completeness here is another, 16-bits (and slightly simpler), solution:
architecture RTL of Ex_7_1_b is
signal x, y0, y1: unsigned(g_BUS_WIDTH - 1 downto 0);
begin
x <= unsigned(i_a);
y0 <= unsigned(i_b) when i_ctrl(1) = '0' else x"0001";
y1 <= not y0 when i_ctrl(0) = '1' else y0;
o_y <= std_logic_vector(x + y1 + i_ctrl(0));
end architecture RTL;
Note: this works only in VHDL 2008 where the addition of an unsigned and a std_logic is defined. If you must use an older version of the VHDL standard use the following, instead:
architecture RTL of Ex_7_1_b is
signal x, y0, y1: unsigned(g_BUS_WIDTH - 1 downto 0);
signal c: natural range 0 to 1;
begin
x <= unsigned(i_a);
y0 <= unsigned(i_b) when i_ctrl(1) = '0' else x"0001";
y1 <= not y0 when i_ctrl(0) = '1' else y0;
c <= 1 when i_ctrl(0) = '1' else 0;
o_y <= std_logic_vector(x + y1 + c);
end architecture RTL;
I want to avoid using inout at the following code.
Is there any way I can do it? For example a helping signal?
entity LA_Unit is
Port ( Cin : in STD_LOGIC;
P : in STD_LOGIC_VECTOR (3 downto 0);
G : in STD_LOGIC_VECTOR (3 downto 0);
C3 : out STD_LOGIC;
C : inout STD_LOGIC_VECTOR (2 downto 0));
end LA_Unit;
architecture Behavioral of LA_Unit is
begin
C(0) <= (P(0) and Cin) xor G(0);
C(1) <= (P(1) and C(0)) xor G(1);
C(2) <= (P(2) and C(1)) xor G(2);
C3 <= (P(3) and C(2)) xor G(3);
end Behavioral;
If the purpose is simply to provide the intermediate value of C as an output to the module, there are different options to avoid inout.
If the tools support VHDL-2008, you can simply change inout to out, and then the C can still be read internally.
If the tools only support VHDL-2002, then you can still change the inout to out, but you then need an internal signal like:
architecture Behavioral of LA_Unit is
signal C_int : std_logic_vector(2 downto 0);
begin
C_int(0) <= (P(0) and Cin) xor G(0);
C_int(1) <= (P(1) and C_int(0)) xor G(1);
C_int(2) <= (P(2) and C_int(1)) xor G(2);
C3 <= (P(3) and C_int(2)) xor G(3);
C <= C_int;
end Behavioral;
As xvan also write, only use inout for toplevel ports on the chip, or for special test-bench use, since inout are not supported internally in a chip.
Use a signal as an intermediate for C(0) and C(1).
Inouts should only be used for hardware io ports, like a gpio port, or the data port on a memory bus.
There are 2 solutions:
Using buffer mode instead of inout.
entity LA_Unit is
Port ( Cin : in STD_LOGIC;
P : in STD_LOGIC_VECTOR (3 downto 0);
G : in STD_LOGIC_VECTOR (3 downto 0);
C3 : out STD_LOGIC;
C : buffer STD_LOGIC_VECTOR (2 downto 0));
end LA_Unit;
architecture Behavioral of LA_Unit is
begin
C(0) <= (P(0) and Cin) xor G(0);
C(1) <= (P(1) and C(0)) xor G(1);
C(2) <= (P(2) and C(1)) xor G(2);
C3 <= (P(3) and C(2)) xor G(3);
end Behavioral;
Some tools have problems with this mode.
An intermediate signal:
entity LA_Unit is
Port ( Cin : in STD_LOGIC;
P : in STD_LOGIC_VECTOR (3 downto 0);
G : in STD_LOGIC_VECTOR (3 downto 0);
C3 : out STD_LOGIC;
C : out STD_LOGIC_VECTOR (2 downto 0)
);
end entity;
architecture rtl of LA_Unit is
signal C_i : STD_LOGIC_VECTOR(3 downto 0);
begin
C_i(0) <= (P(0) and Cin) xor G(0);
C_i(1) <= (P(1) and C_i(0)) xor G(1);
C_i(2) <= (P(2) and C_i(1)) xor G(2);
C_i(3) <= (P(3) and C_i(2)) xor G(3);
C <= C_i(2 downto 0);
C3 <= C_i(3);
end architecture
I coded a CLA 4-Bit adder for a project for EE, and while it'll add Even/Even and Odd/Odd, it won't add A and B if only one of them is Odd.
So basically:
0001 + 0001 = 0010
0001 + 0010 = 0010 (Doesn't detect 0001)
Help is much appreciated!
Code in top-level entity:
signal g1 : unsigned(3 downto 0);
signal g2 : unsigned(3 downto 0);
signal g3 : unsigned(3 downto 0);
signal p1 : unsigned(3 downto 0);
signal p2 : unsigned(3 downto 0);
signal p3 : unsigned(3 downto 0);
signal c1 : unsigned(4 downto 0);
signal c2 : unsigned(4 downto 0);
signal c3 : unsigned(4 downto 0);
signal ci1 : std_logic;
signal ci2 : std_logic;
signal ci3 : std_logic;
signal co1 : std_logic;
signal co2 : std_logic;
signal co3 : std_logic;
signal sum : unsigned(4 downto 0);
signal sum1 : unsigned(3 downto 0);
signal sum2 : unsigned(3 downto 0);
signal sum3 : unsigned(3 downto 0);
signal tn : unsigned(3 downto 0) := "1010";
--A + B
p1 <= unsigned(A xor B);
g1 <= unsigned(A and B);
k1 : CLA1 port map (p1,g1,c1,ci1);
sum1 <= (p1 xor c1(3 downto 0));
co1 <= c1(4);
--A + 1
p2 <= unsigned(A xor "0001");
g2 <= unsigned(A and "0001");
k2 : CLA2 port map (p2,g2,c2,ci2);
sum2 <= (p2 xor c2(3 downto 0));
co2 <= c2(4);
--A + A
p3 <= unsigned(A xor A);
g3 <= unsigned(A and A);
k3 : CLA3 port map (p3,g3,c3,ci3);
sum3 <= (p3 xor c3(3 downto 0));
co3 <= c3(4);
Code in CLA.vhd:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CLA1 is
port (
ci : in std_logic;
p : in unsigned(3 downto 0);
g : in unsigned(3 downto 0);
c : out unsigned(4 downto 0)
);
end CLA1;
architecture Behavioral of CLA1 is
begin
c(0) <= ci;
c(1) <= g(0) or (p(0) and ci);
c(2) <= g(1) or (p(1) and g(0)) or (p(1) and p(0) and ci);
c(3) <= g(2) or (p(2) and g(1)) or (p(2) and p(1) and g(0))
or (p(2) and p(1) and p(0) and ci);
c(4) <= g(3) or (p(3) and g(2)) or (p(3) and p(2) and g(1))
or (p(3) and p(2) and p(1) and g(0)) or (p(3)
and p(2) and p(1) and p(0) and ci);
end Behavioral;
You have done port map in wrong order. i.e. k1 : CLA1 port map (p1,g1,c1,ci1); But it suppose to be k1 : CLA1 port map (ci1,p1,g1,c1);
Do this change and try
You have several errors.
First your code example for the top level is incomplete it's not a Minimal, Complete, and Verifiable example, meaning someone else can't duplicate the error(s) you're encountering.
Second CLA2 and CLA3 appear to have u component declarations (otherwise your code wouldn't analyze, elaborate and simulate). This results in those components being unbound (and their signals not showing up in your node finder). That's correct by using CLA1 instead of CLA2 and CLA3 in k2 and k3.
Third as Aril points out you've messed up the positional port association in the instantiations of k1, k2 and k3 (and as Brian notes this is why we use formal port association). You could also note that k1 (which is bound during elaboration if the entity and architecture pair for CLA1 has previously been analyzed) shouldn't successfully elaborate. It indicates your code snippet doesn't match the description of your errors.
Fix those things and you get better results:
This waveform dump was produced using this stimulus:
STIMULUS:
process
begin
wait for 10 ns;
for i in 0 to 15 loop
B <= std_logic_vector(to_unsigned(i,4));
for j in 0 to 15 loop
A <= std_logic_vector(to_unsigned(j,4));
ci1 <= '0';
ci2 <= '0';
ci3 <= '0';
wait for 10 ns;
ci1 <= '1';
ci2 <= '1';
ci3 <= '1';
wait for 10 ns;
end loop;
end loop;
wait;
end process;
Notice the assumption that A and B are std_logic_vector subtypes, born out by the likes of:
p1 <= unsigned(A xor B);
g1 <= unsigned(A and B);
(All without doing your class work for you while telling you where your errors lie).