VHDL - Carry Look Ahead Adder isn't adding odd and even numbers - vhdl

Question

I coded a CLA 4-Bit adder for a project for EE, and while it'll add Even/Even and Odd/Odd, it won't add A and B if only one of them is Odd.
So basically:
0001 + 0001 = 0010
0001 + 0010 = 0010 (Doesn't detect 0001)
Help is much appreciated!
Code in top-level entity:
signal g1 : unsigned(3 downto 0);
signal g2 : unsigned(3 downto 0);
signal g3 : unsigned(3 downto 0);
signal p1 : unsigned(3 downto 0);
signal p2 : unsigned(3 downto 0);
signal p3 : unsigned(3 downto 0);
signal c1 : unsigned(4 downto 0);
signal c2 : unsigned(4 downto 0);
signal c3 : unsigned(4 downto 0);
signal ci1 : std_logic;
signal ci2 : std_logic;
signal ci3 : std_logic;
signal co1 : std_logic;
signal co2 : std_logic;
signal co3 : std_logic;
signal sum : unsigned(4 downto 0);
signal sum1 : unsigned(3 downto 0);
signal sum2 : unsigned(3 downto 0);
signal sum3 : unsigned(3 downto 0);
signal tn : unsigned(3 downto 0) := "1010";
--A + B
p1 <= unsigned(A xor B);
g1 <= unsigned(A and B);
k1 : CLA1 port map (p1,g1,c1,ci1);
sum1 <= (p1 xor c1(3 downto 0));
co1 <= c1(4);
--A + 1
p2 <= unsigned(A xor "0001");
g2 <= unsigned(A and "0001");
k2 : CLA2 port map (p2,g2,c2,ci2);
sum2 <= (p2 xor c2(3 downto 0));
co2 <= c2(4);
--A + A
p3 <= unsigned(A xor A);
g3 <= unsigned(A and A);
k3 : CLA3 port map (p3,g3,c3,ci3);
sum3 <= (p3 xor c3(3 downto 0));
co3 <= c3(4);
Code in CLA.vhd:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CLA1 is
port (
ci : in std_logic;
p : in unsigned(3 downto 0);
g : in unsigned(3 downto 0);
c : out unsigned(4 downto 0)
);
end CLA1;
architecture Behavioral of CLA1 is
begin
c(0) <= ci;
c(1) <= g(0) or (p(0) and ci);
c(2) <= g(1) or (p(1) and g(0)) or (p(1) and p(0) and ci);
c(3) <= g(2) or (p(2) and g(1)) or (p(2) and p(1) and g(0))
or (p(2) and p(1) and p(0) and ci);
c(4) <= g(3) or (p(3) and g(2)) or (p(3) and p(2) and g(1))
or (p(3) and p(2) and p(1) and g(0)) or (p(3)
and p(2) and p(1) and p(0) and ci);
end Behavioral;

Answer 1

You have done port map in wrong order. i.e. k1 : CLA1 port map (p1,g1,c1,ci1); But it suppose to be k1 : CLA1 port map (ci1,p1,g1,c1);
Do this change and try

Answer 2

You have several errors.
First your code example for the top level is incomplete it's not a Minimal, Complete, and Verifiable example, meaning someone else can't duplicate the error(s) you're encountering.
Second CLA2 and CLA3 appear to have u component declarations (otherwise your code wouldn't analyze, elaborate and simulate). This results in those components being unbound (and their signals not showing up in your node finder). That's correct by using CLA1 instead of CLA2 and CLA3 in k2 and k3.
Third as Aril points out you've messed up the positional port association in the instantiations of k1, k2 and k3 (and as Brian notes this is why we use formal port association). You could also note that k1 (which is bound during elaboration if the entity and architecture pair for CLA1 has previously been analyzed) shouldn't successfully elaborate. It indicates your code snippet doesn't match the description of your errors.
Fix those things and you get better results:
This waveform dump was produced using this stimulus:
STIMULUS:
process
begin
wait for 10 ns;
for i in 0 to 15 loop
B <= std_logic_vector(to_unsigned(i,4));
for j in 0 to 15 loop
A <= std_logic_vector(to_unsigned(j,4));
ci1 <= '0';
ci2 <= '0';
ci3 <= '0';
wait for 10 ns;
ci1 <= '1';
ci2 <= '1';
ci3 <= '1';
wait for 10 ns;
end loop;
end loop;
wait;
end process;
Notice the assumption that A and B are std_logic_vector subtypes, born out by the likes of:
p1 <= unsigned(A xor B);
g1 <= unsigned(A and B);
(All without doing your class work for you while telling you where your errors lie).