Getting correct values for few inputs. Not for all combinations in a 4*4 multiplier - vhdl

I am writing a code for 4*4 multiplier. Although, i am getting correct values for few inputs, it gives me wrong values for few other. Please suggest me what logical errors are present here as i am unable to spot them
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity multiplier is
Port ( a : in std_logic_vector (3 downto 0);
b : in std_logic_vector (3 downto 0);
result : out std_logic_vector (7 downto 0));
end multiplier;
architecture Behavioral of multiplier is
signal P0: std_logic_vector(7 downto 0);
signal P1: std_logic_vector(7 downto 0);
signal SP1: std_logic_vector(7 downto 0);
signal P2: std_logic_vector(7 downto 0);
signal SP2: std_logic_vector(7 downto 0);
signal P3: std_logic_vector(7 downto 0);
component genericadder
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
sum : out std_logic_vector (4 downto 0));
end component;
begin
result(0) <= a(0) and b(0);
P0(0) <= a(0) and b(1);
P0(1) <= a(0) and b(2);
P0(2) <= a(0) and b(3);
P0(3) <='0';
P0(4) <= a(1) and b(0);
P0(5) <= a(1) and b(1);
P0(6) <= a(1) and b(2);
P0(7) <= a(1) and b(3);
ga_for : genericadder
port map(
a =>P0( 3 downto 0),
b =>P0( 7 downto 4),
sum =>P1(4 downto 0));
result(1)<= P1(0);
SP1<= std_logic_vector(shift_right(unsigned(P1),1));
P1(4) <= a(2) and b(0);
P1(5) <= a(2) and b(1);
P1(6) <= a(2) and b(2);
P1(7) <= a(2) and b(3);
ga_for1 : genericadder
port map(
a =>SP1( 3 downto 0),
b =>P1( 7 downto 4),
sum =>P2(4 downto 0));
result(2) <= P2(0);
SP2<= std_logic_vector(shift_right(unsigned(P2),1));
P2(4) <= a(3) and b(0);
P2(5) <= a(3) and b(1);
P2(6) <= a(3) and b(2);
P2(7) <= a(3) and b(3);
ga_for2 : genericadder
port map(
a =>SP2( 3 downto 0),
b =>P2( 7 downto 4),
sum =>P3(4 downto 0));
result(3)<=P3(0);
result(4)<=P3(1);
result(5)<=P3(2);
result(6)<=P3(3);
result(7)<=P3(4);
end Behavioral;
entity genericadder is
generic (
n : Integer:=4
);
Port ( a : in STD_LOGIC_VECTOR (n-1 downto 0);
b : in STD_LOGIC_VECTOR (n-1 downto 0);
sum : out STD_LOGIC_VECTOR (n downto 0));
end genericadder;
--
The genericadder is made up of full adders. Please let me know the error. I am really unable to move ahead

Related

VHDL - Want to create a simple divider

I'm using Vivado 2018.2
I want to make a simple divider, say the input is 153 and the constant is 53. So with 153/53, I want to see 2 and the remainder 47.
The code I have so far errors out (sequential).
entity divider_main is
port(
dividend: in std_logic_vector(7 downto 0);
remainder: out std_logic_vector(5 downto 0);
quotient: out std_logic_vector(2 downto 0)
);
end divider_main;
architecture Behavioral of divider_main is
signal dividend_signal: signed(7 downto 0);
signal remainder_signal: std_logic_vector(5 downto 0);
signal fifty_three: signed(7 downto 0);
signal count: unsigned(2 downto 0);
begin
dividend_signal <= signed(dividend);
fifty_three <= "00011101";
count <= "000";
process(dividend, dividend_signal) is
begin
if dividend_signal < fifty_three then
remainder(5 downto 0) <= std_logic_vector(dividend_signal(5 downto 0));
quotient <= std_logic_vector(count);
dividend_signal <= "00000000";
count(2 downto 0) <= "000";
else
count <= count + 1;
dividend_signal <= dividend_signal - fifty_three;
quotient(2 downto 0) <= "000";
remainder <= "000000";
end if;
end process;
end Behavioral;
I'm new to vhdl so let me know what I am doing wrong!

VHDL: muxes between 11 buses 8 bits wide output

i recieved this question as a pre interview question "Draw a diagram and write the VHDL code for a module that meets the following requirements:
a. Fully synchronous.
b. Muxes between 11 buses where each bus is 8-bits wide.
c. Has 2 cycles of latency.
d. Optimized for maximum clock frequency."
ive been trying to do it myself reading my old notes and assignments i have done in university but i just don't think i'm on the right track with this. i have the code soo far posted below:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Mux is
port(
A: in STD_LOGIC_vector(7 downto 0);
B: in STD_LOGIC_vector(7 downto 0);
C: in STD_LOGIC_vector(7 downto 0);
D: in STD_LOGIC_vector(7 downto 0);
E: in STD_LOGIC_vector(7 downto 0);
F: in STD_LOGIC_vector(7 downto 0);
G: in STD_LOGIC_vector(7 downto 0);
H: in STD_LOGIC_vector(7 downto 0);
I: in STD_LOGIC_vector(7 downto 0);
J: in STD_LOGIC_vector(7 downto 0);
K: in STD_LOGIC_vector(7 downto 0);
S0: in std_LOGIC_vector(3 downto 0);
Z: out STD_LOGIC_vector(7 downto 0)
);
end Mux;
architecture func of Mux is
begin
process (A,B,C,D,E,F,G,H,I,J,K,S0)
begin
if S0="0001" then
Z<= A;
elsif S0="0010" then
Z<= B;
elsif S0="0011" then
Z<= C;
elsif S0="0100" then
Z<= D;
elsif S0="0101" then
Z<= E;
elsif S0="0110" then
Z<= F;
elsif S0="0111" then
Z<= G;
elsif S0="1000" then
Z<= H;
elsif S0="1001" then
Z<= I;
elsif S0="1010" then
Z<= J;
elsif S0="1011" then
Z<= K;
else
Z<=A;
end if;
end process;
end func;
and this is the code i have for my second file:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
entity mux11test is
end entity mux11test;
architecture test of mux11test is
signal T_A: STD_LOGIC_vector(7 downto 0):="00000001";
signal T_B: STD_LOGIC_vector(7 downto 0):="00000010";
signal T_C: STD_LOGIC_vector(7 downto 0):="00000011";
signal T_D: STD_LOGIC_vector(7 downto 0):="00000100";
signal T_E: STD_LOGIC_vector(7 downto 0):="00000101";
signal T_F: STD_LOGIC_vector(7 downto 0):="00000110";
signal T_G: STD_LOGIC_vector(7 downto 0):="00000111";
signal T_H: STD_LOGIC_vector(7 downto 0):="00001000";
signal T_I: STD_LOGIC_vector(7 downto 0):="00001001";
signal T_J: STD_LOGIC_vector(7 downto 0):="00001010";
signal T_K: STD_LOGIC_vector(7 downto 0):="00001011";
signal T_S: STD_LOGIC_vector( 3 downto 0);
signal T_Z: STD_LOGIC_vector(7 downto 0);
component mux11 IS
port(
A: in STD_LOGIC_vector(7 downto 0);
B: in STD_LOGIC_vector(7 downto 0);
C: in STD_LOGIC_vector(7 downto 0);
D: in STD_LOGIC_vector(7 downto 0);
E: in STD_LOGIC_vector(7 downto 0);
F: in STD_LOGIC_vector(7 downto 0);
G: in STD_LOGIC_vector(7 downto 0);
H: in STD_LOGIC_vector(7 downto 0);
I: in STD_LOGIC_vector(7 downto 0);
J: in STD_LOGIC_vector(7 downto 0);
K: in STD_LOGIC_vector(7 downto 0);
S0: in std_LOGIC_vector(3 downto 0);
Z: out STD_LOGIC_vector(7 downto 0)
);
END COMPONENT ;
signal clk : std_LOGIC;
constant clk_period: time:=100ns;
begin
umux: Mux11 port map(T_A,T_B,T_C,T_D,T_E,T_F,T_G,T_H,T_I,T_J,T_K,T_S,T_Z);
clk_process:process
begin
clk<='0';
wait for clk_period/2;
clk <='1';
wait for clk_period/2;
end process;
PROCESS
begin
if T_S="0001" then
T_Z <= T_A ;
elsif T_S="0010" then
T_Z <= T_B ; wait for 100 ns;
elsif T_S="0011" then
T_Z <= T_C ; wait for 100 ns;
elsif T_S="0100" then
T_Z <= T_D ; wait for 100 ns;
elsif T_S="0101" then
T_Z <=T_E ; wait for 100 ns;
elsif T_S="0110" then
T_Z <= T_F ; wait for 100 ns;
elsif T_S="0111" then
T_Z <= T_G ; wait for 100 ns;
elsif T_S="1000" then
T_Z <= T_H ; wait for 100 ns;
elsif T_S="1001" then
T_Z <= T_I ; wait for 100 ns;
elsif T_S="1010" then
T_Z <= T_J ; wait for 100 ns;
elsif T_S="1011" then
T_Z <= T_K ; wait for 100 ns;
wait;
end if;
end PROCESS;
end architecture test;
is there anyone who could tell me if im on the right path and if this is fully synchronous and how would i start implementing or determining 2 cycles of latency?

I try to write a clear answer to help you.
First of all you need a clock in your design let's call it clk.
entity Mux is
port(
clk: in std_logic;
A: in STD_LOGIC_vector(7 downto 0);
B: in STD_LOGIC_vector(7 downto 0);
C: in STD_LOGIC_vector(7 downto 0);
D: in STD_LOGIC_vector(7 downto 0);
E: in STD_LOGIC_vector(7 downto 0);
F: in STD_LOGIC_vector(7 downto 0);
G: in STD_LOGIC_vector(7 downto 0);
H: in STD_LOGIC_vector(7 downto 0);
I: in STD_LOGIC_vector(7 downto 0);
J: in STD_LOGIC_vector(7 downto 0);
K: in STD_LOGIC_vector(7 downto 0);
S0: in std_LOGIC_vector(3 downto 0);
Z: out STD_LOGIC_vector(7 downto 0));
end Mux;
The idea when you use synchronous processes is to always update your values on an edge of your clock. Let's say the rising edge. Thus your processes have to be only sensitive to your input clk.
P : PROCESS (clk)
BEGIN
IF (rising_edge(clk)) THEN
...
END IF;
END PROCESS;
Concerning your multiplexer, your idea was good. Yet I would suggest to use a CASE statement because it is easier to read than IF ELSIF.
CASE S0 IS
WHEN "0001" => Z <= A;
WHEN "0010" => Z <= B;
...
WHEN "1011" => Z <= K;
END CASE;
EDIT : since I forgot to talk about the 2 cycles latency I'll say two words. There you need two intermediate signals (ie Z_i and Z_ii). Z_ii takes Z_i after one clock cycle and Z takes Z_ii after one clock cycle.
Z_ii <= Z_i;
Z <= Z_ii;
Of course you then need to drive Z_i (and not Z) in you process.

Why am I not seeing an output when I synthesize?

I have been working on a lab assignment that is practically complete, but am running into an issue where I am not seeing an output when synthesizing. I have 7 blocks, that when tested individually display the correct output. How is it that I wouldn't get any output at all when using the top module and test bench files? Below is my top module, followed by my test bench as I suspect the problem may be there. I've looked it over and can't pinpoint anything I may have done wrong. Any help would be appreciated.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top_module is port(
x,y : in std_logic_vector(7 downto 0);
opcode : in std_logic_vector(2 downto 0);
z : out std_logic_vector(7 downto 0)
);
end top_module;
architecture behavior of top_module is
signal bwAnd, bwOr, bwXor, add, subtract, bwComplement, mux_in1, mux_in2, mux_in3, mux_in4, mux_in5, mux_in6 : std_logic_vector(7 downto 0);
component BW_And is port(
x,y : in std_logic_vector(7 downto 0);
z1 : out std_logic_vector(7 downto 0)
);
end component;
component BW_Rr is port(
x,y : in std_logic_vector(7 downto 0);
z2 : out std_logic_vector(7 downto 0)
);
end component;
component BW_Xor is port(
x,y : in std_logic_vector(7 downto 0);
z3 : out std_logic_vector(7 downto 0)
);
end component;
component full_adder_8 is port(
x,y : in std_logic_vector(7 downto 0);
cin : in std_logic_vector(7 downto 0) := "00000000";
sum, cout: out std_logic_vector(7 downto 0)
);
end component;
component full_subtractor_8 is port(
x,y : in std_logic_vector(7 downto 0);
cin : in std_logic_vector(7 downto 0) := "11111111";
difference, cout: out std_logic_vector(7 downto 0)
);
end component;
component Complement is port(
x : in std_logic_vector(7 downto 0);
z4 : out std_logic_vector(7 downto 0)
);
end component;
component mux is port(
z1,z2,z3,sum,difference,z4 : in std_logic_vector(7 downto 0);
opcode : in std_logic_vector(2 downto 0);
mux_out : out std_logic_vector(7 downto 0)
);
end component;
begin
--instantiating components and mapping ports
c0: BW_And port map(x => x, y => y, z1 => bwAnd);
c1: BW_Or port map(x => x, y => y, z2 => bwOr);
c2: BW_Xor port map(x => x, y => y, z3 => bwXor);
c3: full_adder_8 port map(x => x, y => y, sum => add);
c4: full_subtractor_8 port map(x => x, y => y, difference => subtract);
c5: Complement port map(x => x, z4 => bwComplement);
c6: mux port map(z1 => mux_in1, z2 => mux_in2, z3 => mux_in3, sum => mux_in4, difference => mux_in5, z4 =>mux_in6, opcode => opcode, mux_out => z);
end behavior;
Test Bench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Lab4 is
end Lab4;
architecture behavior of Lab4 is
component top_module is port(
x,y : in std_logic_vector(7 downto 0);
opcode : in std_logic_vector(2 downto 0);
z : out std_logic_vector(7 downto 0)
);
end component;
signal test_x : std_logic_vector(7 downto 0);
signal test_y : std_logic_vector(7 downto 0);
signal test_opcode : std_logic_vector(2 downto 0) := "000";
signal test_z : std_logic_vector(7 downto 0);
begin
uut: top_module port map (x => test_x, y => test_y, opcode => test_opcode, z => test_z);
sim_proc : process
begin
test_x <= "00010100"; test_y <= "11001111"; test_opcode <= "000";
wait for 100 ns;
test_x <= "00010100"; test_y <= "11001111"; test_opcode <= "001";
wait for 100 ns;
test_x <= "00010100"; test_y <= "11001111"; test_opcode <= "010";
wait for 100 ns;
test_x <= "00010100"; test_y <= "11001111"; test_opcode <= "011";
wait for 100 ns;
test_x <= "00010100"; test_y <= "11001111"; test_opcode <= "100";
wait for 100 ns;
test_x <= "00010100"; test_y <= "11001111"; test_opcode <= "101";
end process;
end behavior;
Entities for each component:
entity BW_And is port(
x,y : in std_logic_vector(7 downto 0);
z1 : out std_logic_vector(7 downto 0)
);
end BW_And;
entity BW_Or is port(
x,y : in std_logic_vector(7 downto 0);
z2 : out std_logic_vector(7 downto 0)
);
end BW_Or;
entity BW_Xor is port(
x,y : in std_logic_vector(7 downto 0);
z3 : out std_logic_vector(7 downto 0)
);
end BW_Xor;
entity full_adder_8 is port(
x,y : in std_logic_vector(7 downto 0);
cin : in std_logic_vector(7 downto 0) := "00000000";
sum, cout: out std_logic_vector(7 downto 0)
);
end full_adder_8;
entity full_subtractor_8 is port(
x,y : in std_logic_vector(7 downto 0);
cin : in std_logic_vector(7 downto 0) := "11111111";
difference, cout: out std_logic_vector(7 downto 0)
);
end full_subtractor_8;
entity Complement is port(
x : in std_logic_vector(7 downto 0);
z4 : out std_logic_vector(7 downto 0)
);
end Complement;
entity mux is port(
z1,z2,z3,sum,difference,z4 : in std_logic_vector(7 downto 0);
opcode : in std_logic_vector(2 downto 0);
mux_out : out std_logic_vector(7 downto 0)
);
end mux;

I realized where my problem was after all. The issue was with my mux file. In my process, I only passed "opcode" neglecting to pass in all of the inputs.
Before:
process (opcode)
.
.
.
end process;
After:
process (z1,z2,z3,sum,difference,z4,opcode)
.
.
.
end process;

Calculate fmax of Altera design

After I finished my design compilation on Quartus, I get multiple result for fmax as shown below. I want to know, what does it means? and How can I calculate the fmax of the all design?.
My design is implementation for the following equation:
for(i = 1; i < 5; i++)
{
T += ( ((Rv[i] - Ru[i]))^2 + ((Iv[i] - Iu[i]))^2 )
}
assume the following:
1. use 4 add-sub, 2 squarer, and eight 21-bit register file(parallel input/output) .
2. finished all operation in 8 clock cycles.
Note: - each adder/subtractor is 21-bit and has a selector pin '1' for add or '0' for sub.
- squarer is 9 bit.
- T is 21 bit.
This is the FSM for my design
According the above, this is my code
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity EDCfunction_TopEntity is
port
(
clk, reset : in std_logic;
Rv1 : in std_logic_vector (8-1 downto 0);
Iv1 : in std_logic_vector (8-1 downto 0);
Ru1 : in std_logic_vector (8-1 downto 0);
Iu1 : in std_logic_vector (8-1 downto 0);
Rv2 : in std_logic_vector (8-1 downto 0);
Iv2 : in std_logic_vector (8-1 downto 0);
Ru2 : in std_logic_vector (8-1 downto 0);
Iu2 : in std_logic_vector (8-1 downto 0);
Rv3 : in std_logic_vector (8-1 downto 0);
Iv3 : in std_logic_vector (8-1 downto 0);
Ru3 : in std_logic_vector (8-1 downto 0);
Iu3 : in std_logic_vector (8-1 downto 0);
Rv4 : in std_logic_vector (8-1 downto 0);
Iv4 : in std_logic_vector (8-1 downto 0);
Ru4 : in std_logic_vector (8-1 downto 0);
Iu4 : in std_logic_vector (8-1 downto 0);
T : out std_logic_vector (21-1 downto 0)
);
end EDCfunction_TopEntity;
architecture behavioral of EDCfunction_TopEntity is
type clock_state is (zero, zero_clk2, one, two, two_clk2, three, three_clk2, four, four_clk2, five, six, seven, eight);
type add_sub_type is array (4-1 downto 0) of std_logic_vector (21-1 downto 0);
type squarer_in_type is array (2-1 downto 0) of std_logic_vector (9-1 downto 0);
type squarer_out_type is array (2-1 downto 0) of std_logic_vector (18-1 downto 0);
signal cc_state, cn_state : clock_state;
signal clk_reg_file, reset_reg_file, s_wr_en : std_logic;
signal add_sub_flage, state_mux : std_logic_vector (4-1 downto 0);
signal dataa_add_sub, datab_add_sub, result_add_sub : add_sub_type;
signal dataa_squarer : squarer_in_type;
signal result_squarer : squarer_out_type;
signal w_addr_reg_file, r_addr_reg_file : std_logic_vector (8-1 downto 0);
signal s_w_data_0, s_w_data_1, s_w_data_2, s_w_data_3, s_w_data_4, s_w_data_5, s_w_data_6, s_w_data_7,
s_r_data_0, s_r_data_1, s_r_data_2, s_r_data_3, s_r_data_4, s_r_data_5, s_r_data_6, s_r_data_7
: std_logic_vector (21-1 downto 0);
alias R0 is s_w_data_0(21-1 downto 0);
alias R0H is s_w_data_0(21-1 downto 10);
alias R0L is s_w_data_0(9 downto 0);
alias R1 is s_w_data_1(21-1 downto 0);
alias R1H is s_w_data_1(21-1 downto 10);
alias R1L is s_w_data_1(9 downto 0);
alias R2 is s_w_data_2(21-1 downto 0);
alias R2H is s_w_data_2(21-1 downto 10);
alias R2L is s_w_data_2(9 downto 0);
alias R3 is s_w_data_3(21-1 downto 0);
alias R3H is s_w_data_3(21-1 downto 10);
alias R3L is s_w_data_3(9 downto 0);
alias R4 is s_w_data_4(21-1 downto 0);
alias R4H is s_w_data_4(21-1 downto 10);
alias R4L is s_w_data_4(9 downto 0);
alias R5 is s_w_data_5(21-1 downto 0);
alias R5H is s_w_data_5(21-1 downto 10);
alias R5L is s_w_data_5(9 downto 0);
alias R6 is s_w_data_6(21-1 downto 0);
alias R6H is s_w_data_6(21-1 downto 10);
alias R6L is s_w_data_6(9 downto 0);
alias R7 is s_w_data_7(21-1 downto 0);
alias R7H is s_w_data_7(21-1 downto 10);
alias R7L is s_w_data_7(9 downto 0);
component lpm_adder_subtractor
port
(
add_sub : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (20 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (20 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (20 DOWNTO 0)
);
end component;
component lpm_squarer
PORT
(
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (17 DOWNTO 0)
);
end component;
component register_file
port
(
clk, reset : in std_logic;
wr_en : in std_logic;
w_addr : in std_logic_vector (8-1 downto 0);
w_data_0 : in std_logic_vector (21-1 downto 0);
w_data_1 : in std_logic_vector (21-1 downto 0);
w_data_2 : in std_logic_vector (21-1 downto 0);
w_data_3 : in std_logic_vector (21-1 downto 0);
w_data_4 : in std_logic_vector (21-1 downto 0);
w_data_5 : in std_logic_vector (21-1 downto 0);
w_data_6 : in std_logic_vector (21-1 downto 0);
w_data_7 : in std_logic_vector (21-1 downto 0);
r_addr : in std_logic_vector (8-1 downto 0);
r_data_0 : out std_logic_vector (21-1 downto 0);
r_data_1 : out std_logic_vector (21-1 downto 0);
r_data_2 : out std_logic_vector (21-1 downto 0);
r_data_3 : out std_logic_vector (21-1 downto 0);
r_data_4 : out std_logic_vector (21-1 downto 0);
r_data_5 : out std_logic_vector (21-1 downto 0);
r_data_6 : out std_logic_vector (21-1 downto 0);
r_data_7 : out std_logic_vector (21-1 downto 0)
);
end component;
begin
A0 : lpm_adder_subtractor port map (add_sub_flage(0), dataa_add_sub(0), datab_add_sub(0), result_add_sub(0));
A1 : lpm_adder_subtractor port map (add_sub_flage(1), dataa_add_sub(1), datab_add_sub(1), result_add_sub(1));
A2 : lpm_adder_subtractor port map (add_sub_flage(2), dataa_add_sub(2), datab_add_sub(2), result_add_sub(2));
A3 : lpm_adder_subtractor port map (add_sub_flage(3), dataa_add_sub(3), datab_add_sub(3), result_add_sub(3));
S0 : lpm_squarer port map (dataa_squarer(0), result_squarer(0));
S1 : lpm_squarer port map (dataa_squarer(1), result_squarer(1));
U0 : register_file port map (clk, reset_reg_file, s_wr_en, w_addr_reg_file, s_w_data_0, s_w_data_1, s_w_data_2,
s_w_data_3, s_w_data_4, s_w_data_5, s_w_data_6, s_w_data_7, r_addr_reg_file,
s_r_data_0, s_r_data_1, s_r_data_2, s_r_data_3, s_r_data_4, s_r_data_5, s_r_data_6,
s_r_data_7);
process (cc_state, reset, Rv1, Iv1, Ru1, Iu1, Rv2, Iv2, Ru2, Iu2, Rv3, Iv3, Ru3, Iu3, Rv4, Iv4, Ru4, Iu4)
begin
case cc_state is
when zero =>
s_wr_en <= '1';
w_addr_reg_file <= "11111111";
R0H <= std_logic_vector(resize(signed(Rv1), R0H'length));
R0L <= std_logic_vector(resize(signed(Ru1), R0L'length));
R1H <= std_logic_vector(resize(signed(Iv1), R1H'length));
R1L <= std_logic_vector(resize(signed(Iu1), R1L'length));
R2H <= std_logic_vector(resize(signed(Rv2), R2H'length));
R2L <= std_logic_vector(resize(signed(Ru2), R2L'length));
R3H <= std_logic_vector(resize(signed(Iv2), R3H'length));
R3L <= std_logic_vector(resize(signed(Iu2), R3L'length));
R4H <= std_logic_vector(resize(signed(Rv3), R4H'length));
R4L <= std_logic_vector(resize(signed(Ru3), R4L'length));
R5H <= std_logic_vector(resize(signed(Iv3), R5H'length));
R5L <= std_logic_vector(resize(signed(Iu3), R5L'length));
R6H <= std_logic_vector(resize(signed(Rv4), R6H'length));
R6L <= std_logic_vector(resize(signed(Ru4), R6L'length));
R7H <= std_logic_vector(resize(signed(Iv4), R7H'length));
R7L <= std_logic_vector(resize(signed(Iu4), R7L'length));
--clk_reg_file <= '1';
--T <= result_add_sub(0);
cn_state <= zero_clk2;
when zero_clk2 =>
r_addr_reg_file <= "11111111";
cn_state <= one;
when one =>
s_wr_en <= '0';
--w_addr_reg_file <= "00001111";
add_sub_flage(0) <= '0';
add_sub_flage(1) <= '0';
add_sub_flage(2) <= '0';
add_sub_flage(3) <= '0';
--r_addr_reg_file <= "00001111";
dataa_add_sub(0) <= std_logic_vector(resize(signed(s_r_data_0 (21-1 downto 10)), dataa_add_sub(0)'length));
datab_add_sub(0) <= std_logic_vector(resize(signed(s_r_data_0 (9 downto 0)), dataa_add_sub(0)'length));
--s_w_data_0 <= result_add_sub(0);
--w_addr_reg_file <= "00000001";
dataa_add_sub(1) <= std_logic_vector(resize(signed(s_r_data_1 (21-1 downto 10)), dataa_add_sub(1)'length));
datab_add_sub(1) <= std_logic_vector(resize(signed(s_r_data_1 (9 downto 0)), dataa_add_sub(1)'length));
--s_w_data_1 <= result_add_sub(1);
--w_addr_reg_file <= "00000010";
dataa_add_sub(2) <= std_logic_vector(resize(signed(s_r_data_2 (21-1 downto 10)), dataa_add_sub(2)'length));
datab_add_sub(2) <= std_logic_vector(resize(signed(s_r_data_2 (9 downto 0)), dataa_add_sub(2)'length));
--s_w_data_2 <= result_add_sub(2);
--w_addr_reg_file <= "00000100";
dataa_add_sub(3) <= std_logic_vector(resize(signed(s_r_data_3 (21-1 downto 10)), dataa_add_sub(3)'length));
datab_add_sub(3) <= std_logic_vector(resize(signed(s_r_data_3 (9 downto 0)), dataa_add_sub(3)'length));
--s_w_data_3 <= result_add_sub(3);
--w_addr_reg_file <= "00001000";
--T <= result_add_sub(3);
--clk_reg_file <= '1';
--r_addr_reg_file <= "11110000";
cn_state <= two;
--state_mux <= "0001";
when two =>
s_wr_en <= '1';
w_addr_reg_file <= "00001111";
R0 <= result_add_sub(0);
R1 <= result_add_sub(1);
R2 <= result_add_sub(2);
R3 <= result_add_sub(3);
dataa_squarer(0) <= result_add_sub(0) (9-1 downto 0);
dataa_squarer(1) <= result_add_sub(1) (9-1 downto 0);
dataa_add_sub(0) <= std_logic_vector(resize(signed(s_r_data_4 (21-1 downto 10)), dataa_add_sub(0)'length));
datab_add_sub(0) <= std_logic_vector(resize(signed(s_r_data_4 (9 downto 0)), dataa_add_sub(0)'length));
dataa_add_sub(1) <= std_logic_vector(resize(signed(s_r_data_5 (21-1 downto 10)), dataa_add_sub(1)'length));
datab_add_sub(1) <= std_logic_vector(resize(signed(s_r_data_5 (9 downto 0)), dataa_add_sub(1)'length));
dataa_add_sub(2) <= std_logic_vector(resize(signed(s_r_data_6 (21-1 downto 10)), dataa_add_sub(2)'length));
datab_add_sub(2) <= std_logic_vector(resize(signed(s_r_data_6 (9 downto 0)), dataa_add_sub(2)'length));
dataa_add_sub(3) <= std_logic_vector(resize(signed(s_r_data_7 (21-1 downto 10)), dataa_add_sub(3)'length));
datab_add_sub(3) <= std_logic_vector(resize(signed(s_r_data_7 (9 downto 0)), dataa_add_sub(3)'length));
cn_state <= two_clk2;
when two_clk2 =>
cn_state <= three;
when three =>
--s_wr_en <= '1';
w_addr_reg_file <= "11110011";
R0 <= std_logic_vector(resize(signed(result_squarer(0)), R0'length));
R1 <= std_logic_vector(resize(signed(result_squarer(1)), R0'length));
R4 <= result_add_sub(0);
R5 <= result_add_sub(1);
R6 <= result_add_sub(2);
R7 <= result_add_sub(3);
add_sub_flage(0) <= '1';
dataa_add_sub(0) <= std_logic_vector(resize(signed(result_squarer(0)), dataa_add_sub(0)'length));
datab_add_sub(0) <= std_logic_vector(resize(signed(result_squarer(1)), datab_add_sub(0)'length));
dataa_squarer(0) <= s_r_data_2 (9-1 downto 0);
dataa_squarer(1) <= s_r_data_3 (9-1 downto 0);
cn_state <= three_clk2;
when three_clk2 =>
cn_state <= four;
when four =>
w_addr_reg_file <= "00000110";
R0 <= result_add_sub(0);
R1 <= std_logic_vector(resize(signed(result_squarer(0)), R0'length));
R2 <= std_logic_vector(resize(signed(result_squarer(1)), R0'length));
add_sub_flage(1) <= '1';
dataa_add_sub(1) <= std_logic_vector(resize(signed(result_squarer(0)), dataa_add_sub(1)'length));
datab_add_sub(1) <= std_logic_vector(resize(signed(result_squarer(1)), datab_add_sub(1)'length));
dataa_squarer(0) <= s_r_data_4 (9-1 downto 0);
dataa_squarer(1) <= s_r_data_5 (9-1 downto 0);
cn_state <= four_clk2;
when four_clk2 =>
cn_state <= five;
when five =>
w_addr_reg_file <= "00001110";
R1 <= result_add_sub(1);
R2 <= std_logic_vector(resize(signed(result_squarer(0)), R2'length));
R3 <= std_logic_vector(resize(signed(result_squarer(1)), R3'length));
add_sub_flage(2) <= '1';
dataa_add_sub(0) <= R0;
datab_add_sub(0) <= result_add_sub(1);
dataa_add_sub(2) <= std_logic_vector(resize(signed(result_squarer(0)), dataa_add_sub(2)'length));
datab_add_sub(2) <= std_logic_vector(resize(signed(result_squarer(1)), datab_add_sub(2)'length));
dataa_squarer(0) <= s_r_data_6 (9-1 downto 0);
dataa_squarer(1) <= s_r_data_7 (9-1 downto 0);
cn_state <= six;
when six =>
w_addr_reg_file <= "00001111";
R0 <= result_add_sub(0);
R1 <= result_add_sub(2);
R2 <= std_logic_vector(resize(signed(result_squarer(0)), R2'length));
R3 <= std_logic_vector(resize(signed(result_squarer(1)), R3'length));
add_sub_flage(3) <= '1';
dataa_add_sub(0) <= result_add_sub(0);
datab_add_sub(0) <= result_add_sub(2);
dataa_add_sub(3) <= std_logic_vector(resize(signed(result_squarer(0)), dataa_add_sub(2)'length));
datab_add_sub(3) <= std_logic_vector(resize(signed(result_squarer(1)), datab_add_sub(2)'length));
cn_state <= seven;
when seven =>
w_addr_reg_file <= "00000011";
R0 <= result_add_sub(0);
R1 <= result_add_sub(3);
dataa_add_sub(0) <= result_add_sub(0);
datab_add_sub(0) <= result_add_sub(3);
--R0 <= result_add_sub(0);
--T <= result_add_sub(0);
cn_state <= eight;
when eight =>
w_addr_reg_file <= "00000001";
R0 <= result_add_sub(0);
T <= result_add_sub(0);
cn_state <= zero;
end case;
--if(state_mux = "0001") then
--end if;
end process;
process (clk, reset)
begin
reset_reg_file <= reset;
if(reset = '1') then
cc_state <= zero;
elsif (clk'event and clk = '1') then
cc_state <= cn_state;
end if;
end process;
end behavioral;
Any help,
Regards

cc_state is presumably being treated as a clock in your 'combinatorial' process, but your code is too complex to make it obvious why. It's likely that you're reading something before assigning to it, which implies clocked functionality. Your synthesis report will tell you what cc_state is clocking, and why.
You need to rewrite your code to simplify it - this is way too complex. Move out your LPM code into a new module which is unclocked. This should be controlled by your 3-bit state signal. Instantiate this in your top-level clocked module, which should contain only the register file, and a simplified FSM.
You should also think about:
Move the stuff in the architecture declarative region into a package
Make use of subtypes to get rid of all the std_logic_vector stuff
If you end up with a case statement in your combinatorial module, make sure that you set default values for all outputs, or assign in all branches (your existing code doesn't assign to s_wr_en in all branches)
If it still doesn't work, post a much simpler question. Your algorithm isn't relevant to the question.

8 bit Ripple carry adder Port mappinng in VHDL

I wrote the code for 8 bit adder by usign 4 bit carry look ahead adder. i instantiated the 4 bit caryy look ahed adder using port map. but i think i am wrong for port mapping . plese any one can hel me , how can i correct the port mapping ..
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity adder_4_bit is
Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0);
s : out STD_LOGIC_VECTOR (3 downto 0);
cout: out STD_LOGIC);
end adder_4_bit;
architecture Behavioral of adder_4_bit is
signal g, p, c, b1: STD_LOGIC_VECTOR(3 downto 0);
begin
g <= a and b;
p <= a xor b;
s(0) <= p(0) ;
c(0) <= g(0) or p(0) ;
s(1) <= p(1) xor c(0);
c(1) <= g(1) or (p(1) and g(0)) or (p(1) and p(0));
s(2) <= p(2) xor c(1);
c(2) <= g(2) or (p(2) and g(1)) or (p(2) and p(1) and g(0)) or (p(2) and p(1) and p(0));
s(3) <= p(3) xor c(2);
c(3) <= g(3) or (p(3) and g(2)) or (p(3) and p(2) and g(1)) or (p(3) and p(2) and p(1) and g(0)) or (p(3) and p(2) and p(1) and p(0));
cout <= c(3);
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--********************************************************--
entity Adder_8_bit is
Port (
a,b : in STD_LOGIC_VECTOR (7 downto 0);
s : out STD_LOGIC_VECTOR (7 downto 0);
cout: out STD_LOGIC
);
end Adder_8_bit;k
---******************---
architecture Behavioral of Adder_8_bit is
component adder_4_bit is
Port (
A,B : in STD_LOGIC_VECTOR (3 downto 0);
S: out STD_LOGIC_VECTOR (3 downto 0);
cout: out STD_LOGIC
);
end component;
----
signal a1 ,b1 : STD_LOGIC_VECTOR (7 downto 0);
signal SUM : STD_LOGIC_VECTOR (7 downto 0);
begin
four_bit_adder1: adder_4_bit port map ( a1(3 downto 0) ,b1(3 downto 0) , SUM (3 downto 0) , cout) ;
four_bit_adder2: adder_4_bit port map ( a1(7 downto 4) ,b1(7 downto 4) , SUM (7 downto 4) , cout ) ;
end Behavioral;

You connect the signal cout to two drivers:
four_bit_adder1: adder_4_bit port map ( a1(3 downto 0) ,b1(3 downto 0) , SUM (3 downto 0) , cout);
four_bit_adder2: adder_4_bit port map ( a1(7 downto 4) ,b1(7 downto 4) , SUM (7 downto 4) , cout );
This is wrong, as the toplevel cout should have only 1 source, in this case the four_bit_adder2.
Your 4 bits adder also requires a carry in, otherwise it is impossible to chain two of them to form a 8 bits adder. The first adder's carry in is '0', the second adder's carry in is the first adder's carry out.

Resources