I want use internal signal of tag_mem entity in vivado in Test Bench.
Line with error in TB_tag_mem.vhd:
alias chTagMem is << signal .tag_mem.chTagMem : chTagMem_line >>;
Signal in tag_mem (tag_mem.vhd):
type chTagMem_line is array (natural range <>) of std_logic_vector (TAG_WIDTH downto 0);
signal chTagMem : chTagMem_line(CHAN_CNT - 1 downto 0);
When I run simulation, I see error in elaborate.log:
Starting static elaboration
ERROR: [VRFC 10-3763] type error near 'chtagmem' ; expected type 'chtagmem_line' [C:/Users/Mixen/CBDD/tag_mem/tag_mem.srcs/sim_1/new/TB_tag_mem.vhd:68]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit tb_tag_mem in library work failed.
How fix this?
Reproduce
TB_tag_mem.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.NUMERIC_STD.all;
entity TB_tag_mem is
-- Port ( );
end TB_tag_mem;
architecture Test of TB_tag_mem is
component tag_mem is
Port (
clk : in STD_LOGIC
);
end component;
-- for check
type chTagMem_line is array (natural range <>) of std_logic_vector (5 downto 0);
alias chTagMem is << signal .tag_mem.chTagMem : chTagMem_line >>;
begin
sim: process begin
report "TEST: Init";
wait;
end process sim;
end Test;
tag_mem.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity tag_mem is
Generic (
WIDTH: integer := 5
);
Port (
clk : in STD_LOGIC
);
end tag_mem;
architecture Behavioral of tag_mem is
type chTagMem_line is array (natural range <>) of std_logic_vector (WIDTH downto 0);
signal chTagMem : chTagMem_line(4 downto 0);
begin
end Behavioral;
Here is my code for paralel in serial out shif register. I get error Near text "process"; expecting "if" and i cant fix this.
Here is my code
library ieee;
use ieee.std_logic_1164.all;
entity shiftreg is
port(
sl:in std_logic;
clk:in std_logic;
data:in std_logic_vector(3 downto 0);
q:out std_logic
);
end shiftreg;
architecture myarch of shiftreg is
signal q1:std_logic_vector(3 downto 0);
begin
process(sl,clk,data)
begin
if(sl='0') then
q1<=data;
else if(sl='1' and rising_edge(clk)) then
q<=q1(3);
q1(3)<=q1(2);
q1(2)<=q1(1);
q1(1)<=q1(0);
q1(0)<="0";
end if;
end process;
end myarch;
I've created the following fsm to control a fir filter but I'm getting two errors while compiling.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
entity fsm is
generic (n: integer:=4);
port( clk: in STD_LOGIC;
rst: in STD_LOGIC;
a: out STD_LOGIC_VECTOR(2*n-1 downto 0));
end fsm;
architecture fsm_struct of fsm is
type state_type is (state0, state1, state2);
signal state: state_type;
signal rstff, rom_enable, ram_read_enable, ram_write_enable: STD_LOGIC;
component filter_rom is
generic (n: integer);
port ( clk: in STD_LOGIC;
rstff: in STD_LOGIC;
rom_enable : in STD_LOGIC;
ram_read_enable : in STD_LOGIC;
ram_write_enable : in STD_LOGIC;
a: out STD_LOGIC_VECTOR(2*n-1 downto 0));
end component;
begin
process(clk,rst)
variable delay1:integer:=0;
variable delay2:integer:=0;
variable delay3:integer:=0;
begin
if rst='1' then
state<=state0;
else if rising_edge(clk) then
case state is
when state0 => --initialize & input data
rom_enable<='1';
rstff<='1';
if delay1=1 then
rstff<='0';
state<=state1;
delay2:=0;
else
delay1:=delay1+1;
state<=state0;
end if;
when state1 => --write data to ram
if delay2=2 then
ram_write_enable<='1';
state<=state2;
delay3:=0;
else
delay2:=delay2+1;
state<=state1;
end if;
when state2 => --read data from ram
if delay3=1 then
ram_read_enable<='1';
state<=state0;
delay1:=0;
else
delay3:=delay3+1;
state<=state2;
end if;
end case;
end if;
end process;
filter0: filter_memory generic map(n=>n) port map(clk,rstff,rom_enable,ram_read_enable,ram_write_enable,a);
end fsm_struct;
The errors I'm getting are: Line 83: Syntax error near "process",
Line 85: Syntax error near "generic". at the end of the program. I know that my code won't even compile to any of your machines as my filter is not defined, but I need some help from a fresh set of eyes.
I used 'else if' instead of 'elsif' and it didn't compile.
filter0: filter_memory generic map(n=>n) but your component name is filter_rom
try
filter0: filter_rom generic map(n=>n)
If you changed else if to elsif change it here also.
It compiles in Vivado 2017.4
this is the code and saved it as IR.vhd, while the name of the project is saved as "8051"
when i try to compile a vhdl program in altera it is showing "Error (12007): Top-level design entity "8051" is undefined
" ... what does it mean ?
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity IR is
port(clk,rst,pb1:in std_logic;
irreg:in std_logic_vector(15 downto 0);
ops:out std_logic_vector(2 downto 0);
modes:out std_logic;
loc1:out std_logic_vector(3 downto 0);
loc2ordata:out std_logic_vector(7 downto 0));
end IR;
architecture rtl of IR is
signal ireg: std_logic_vector(15 downto 0);
begin
process (pb1)
begin
if(pb1='0')then --I am going to set up to feed in one instruction at a time
ireg<=irreg; --the instruction is executed when pb1 is pressed
end if;
end process;
ops<=ireg(15 downto 13);
modes<=ireg(12);
loc1<=ireg(11 downto 8);
loc2ordata<=ireg(7 downto 0);
end rtl;
Something I have noticed is that the top level entity name needs to be the same as the file name and module name. So if you called the top level IR, the file probably needs to be IR.v. Now I never capitalize my file names so I don't actually know if capitalization matching is important.
I'm using Quartus prime edition v15.1 for writing a register file and I need to use the numeric_std_unsigned package. On compiling, there's an error saying
Error (10481): VHDL Use Clause error : design library "IEEE" does not contain primary unit "NUMERIC_STD_unsigned". Verify that the primary unit exists in the library and has been successfully compiled.
How doesn't the IEEE library have the numeric_std_unsigned package? I've searched a lot and found that IEEE actually supports it. And if so, how can I firstly download the package and install it to the compiler or add it to my project?
EDIT
Here's my code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std_unsigned.all;
entity regfile is
port( clk: in STD_LOGIC;
regwrite: in STD_LOGIC;
rs, rt, rd: in STD_LOGIC_VECTOR(1 downto 0);
data_in: in STD_LOGIC_VECTOR(15 downto 0);
rd1, rd2: out STD_LOGIC_VECTOR(15 downto 0));
end;
architecture behave of regfile is
type registerFile is array (3 downto 0) of STD_LOGIC_VECTOR(15 downto 0);
signal registers: registerFile;
begin
process(clk) begin
if rising_edge(clk) then
if regwrite='1' then
registers(to_integer(unsigned(rd))) <= data_in;
end if;
end if;
end process;
process(all)
begin
if (to_integer(rs)=0)
then rd1 <= X"0000";
else rd1 <= registers(to_integer(unsigned(rs)));
end if;
if (to_integer(rt)=0)
then rd2 <= X"0000";
else rd2 <= registers(to_integer(unsigned(rt)));
end if;
end process;
end;
When I use IEEE.numeric_std_unsigned.all the compiler reports the error I posted above.
And when I use IEEE_numeric_std.all the compiler reports
can't determine type of object at to_integer
more than one Use Clause imports a declaration of simple name unsigned -- none of the declarations are directly visible
Once you edited your question to provide a Minimal, Complete, and Verifiable example the error is clearly visible.
Remove the use clause with std_logic_arith, it's incompatible with the unsigned declaration package numeric_std_unsigned uses (referenced from a use clause invoking ieee.numeric_std.all). In it's place use
use ieee.numeric_std.all;
Some of the to_integer function calls found in your regfile architecture have a signature of [STD_ULOGIC_VECTOR return NATURAL].
(STD_ULOGIC_VECTOR is the base type for resolved subtype STD_LOGIC_VECTOR in package std_logic_1164 in VHDL -2008).
Some to_integer conversion function calls (e.g. to_integer(rs)) require package numeric_std_unsigned.
Those depending on package numeric_std (e.g. registers(to_integer(unsigned(rs))) also depend on a visible declaration for type unsigned being the same as the type declaration of the same name being visible in package numeric_std (referenced in a use clause in package numeric_std_unsigned).
In VHDL each declaration is unique even if they have the same name. Which one you are referencing is governed by visibility rules.
Before changing the use clause only the unsigned type declared in the Synopsys package was visible in your entity and architecture pair.
After switching std_logic_arith to numeric_std your code analyzes with a -2008 compliant VHDL implementation:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- use IEEE.std_logic_arith.all;
use ieee.numeric_std.all;
use IEEE.numeric_std_unsigned.all;
entity regfile is
port (
clk: in STD_LOGIC;
regwrite: in STD_LOGIC;
rs, rt, rd: in STD_LOGIC_VECTOR(1 downto 0);
data_in: in STD_LOGIC_VECTOR(15 downto 0);
rd1, rd2: out STD_LOGIC_VECTOR(15 downto 0)
);
end entity;
architecture behave of regfile is
type registerFile is array (3 downto 0) of STD_LOGIC_VECTOR(15 downto 0);
signal registers: registerFile;
begin
process (clk)
begin
if rising_edge(clk) then
if regwrite = '1' then
registers(to_integer(unsigned(rd))) <= data_in;
end if;
end if;
end process;
process (all)
begin
if to_integer(rs) = 0 then
rd1 <= X"0000";
else
rd1 <= registers(to_integer(unsigned(rs)));
end if;
if to_integer(rt) = 0 then
rd2 <= X"0000";
else
rd2 <= registers(to_integer(unsigned(rt)));
end if;
end process;
end architecture;
Style changes not withstanding the only change is the use clause.
You could remove the dependency on package numeric_std by changing the to_integer function calls with the signature [UNSIGNED return NATURAL] to [STD_ULOGIC_VECTOR return NATURAL]:
library ieee;
use ieee.std_logic_1164.all;
-- use IEEE.std_logic_arith.all;
-- use ieee.numeric_std.all;
use IEEE.numeric_std_unsigned.all;
entity regfile is
port (
clk: in std_logic;
regwrite: in std_logic;
rs, rt, rd: in std_logic_vector(1 downto 0);
data_in: in std_logic_vector(15 downto 0);
rd1, rd2: out STD_LOGIC_VECTOR(15 downto 0)
);
end entity;
architecture behave of regfile is
type registerFile is array (3 downto 0) of STD_LOGIC_VECTOR(15 downto 0);
signal registers: registerFile;
begin
process (clk)
begin
if rising_edge(clk) then
if regwrite = '1' then
registers(to_integer(rd)) <= data_in;
end if;
end if;
end process;
process (all)
begin
if to_integer(rs) = 0 then
rd1 <= X"0000";
else
rd1 <= registers(to_integer(rs));
end if;
if to_integer(rt) = 0 then
rd2 <= X"0000";
else
rd2 <= registers(to_integer(rt));
end if;
end process;
end architecture;
Note we've gotten rid of the use clause with package numeric_std and dropped some type conversions for generating the indexes for indexed names selecting registers elements for writes to the register file as well as both read ports.
Both these modifications to your code example analyze, elaborate and simulate telling us the indexes work correctly. The second one using only package numeric_std_unsigned enhances readability.
And of course if your VHDL tool is actually missing package numeric_std_unsigned and it isn't cured by re-installation or updating the Quartus tools you could use a -1993 compliant design description:
library ieee;
use ieee.std_logic_1164.all;
-- use IEEE.std_logic_arith.all;
use ieee.numeric_std.all;
-- use IEEE.numeric_std_unsigned.all;
entity regfile is
port (
clk: in std_logic;
regwrite: in std_logic;
rs, rt, rd: in std_logic_vector(1 downto 0);
data_in: in std_logic_vector(15 downto 0);
rd1, rd2: out STD_LOGIC_VECTOR(15 downto 0)
);
end entity;
architecture behave of regfile is
type registerFile is array (3 downto 0) of STD_LOGIC_VECTOR(15 downto 0);
signal registers: registerFile;
begin
process (clk)
begin
if rising_edge(clk) then
if regwrite = '1' then
registers(to_integer(unsigned(rd))) <= data_in;
end if;
end if;
end process;
process (rs, rt) -- (all)
begin
if to_integer(unsigned(rs)) = 0 then
rd1 <= X"0000";
else
rd1 <= registers(to_integer(unsigned(rs)));
end if;
if to_integer(unsigned(rt)) = 0 then
rd2 <= X"0000";
else
rd2 <= registers(to_integer(unsigned(rt)));
end if;
end process;
end architecture;
Where the process sensitivity list is manually specified and all to_integer calls are from package numeric_std, requiring unsigned type conversions for std_logic_vector values.
(And this analyzes, elaborates and simulates).
I assume you mean the unsigned type of the numeric_std package in the ieee library.
library ieee;
use ieee.numeric_std.all;
...
signal foo : unsigned(7 downto 0);
or
library ieee;
use ieee.numric_std;
...
signal bar : numeric_std.unsigned(7 downto 0);
The installation folder of Quartus Prime 15.1 actually contains a file called numeric_std_unsigned_vhdl2008.vhd which defines the package numeric_std_unsigned and its body. But, apparently the synthesizer does not support it.
The Quartus Prime Standard Handbook v15.1.1, Volume 1 gives in Section 16 under "VHDL Synthesis Support" -> "VHDL-2008 Support" a link to this online help page. At the time of writing this answer, the list of supported VHDL'08 features does not reference Section 16.8.5 of the VHDL'08 Standard which defines the package numeric_std_unsigned. There is also no reference to Appendix A.2.4.
The following sub-section in the Quartus manual states further:
The Quartus Prime software includes the standard IEEE libraries and several vendor-specific VHDL libraries.
The IEEE library includes the standard VHDL packages std_logic_1164, numeric_std, numeric_bit, and math_real.
Given that, you must revert back to using the numeric_std package. But, this package defines the type unsigned which is also defined in std_logic_arith. You should not use the non-standard std_logic_arith package from Synopsys anymore.
Thus, you have to use the package numeric_std instead of both numeric_std_unsigned and std_logic_arith.. Then you have to convert all std_logic_vector to unsigned first, before passing them as an argument to the function to_integer, e.g.:
to_integer(unsigned(rs))
instead of
to_integer(rs)