I've created the following fsm to control a fir filter but I'm getting two errors while compiling.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
entity fsm is
generic (n: integer:=4);
port( clk: in STD_LOGIC;
rst: in STD_LOGIC;
a: out STD_LOGIC_VECTOR(2*n-1 downto 0));
end fsm;
architecture fsm_struct of fsm is
type state_type is (state0, state1, state2);
signal state: state_type;
signal rstff, rom_enable, ram_read_enable, ram_write_enable: STD_LOGIC;
component filter_rom is
generic (n: integer);
port ( clk: in STD_LOGIC;
rstff: in STD_LOGIC;
rom_enable : in STD_LOGIC;
ram_read_enable : in STD_LOGIC;
ram_write_enable : in STD_LOGIC;
a: out STD_LOGIC_VECTOR(2*n-1 downto 0));
end component;
begin
process(clk,rst)
variable delay1:integer:=0;
variable delay2:integer:=0;
variable delay3:integer:=0;
begin
if rst='1' then
state<=state0;
else if rising_edge(clk) then
case state is
when state0 => --initialize & input data
rom_enable<='1';
rstff<='1';
if delay1=1 then
rstff<='0';
state<=state1;
delay2:=0;
else
delay1:=delay1+1;
state<=state0;
end if;
when state1 => --write data to ram
if delay2=2 then
ram_write_enable<='1';
state<=state2;
delay3:=0;
else
delay2:=delay2+1;
state<=state1;
end if;
when state2 => --read data from ram
if delay3=1 then
ram_read_enable<='1';
state<=state0;
delay1:=0;
else
delay3:=delay3+1;
state<=state2;
end if;
end case;
end if;
end process;
filter0: filter_memory generic map(n=>n) port map(clk,rstff,rom_enable,ram_read_enable,ram_write_enable,a);
end fsm_struct;
The errors I'm getting are: Line 83: Syntax error near "process",
Line 85: Syntax error near "generic". at the end of the program. I know that my code won't even compile to any of your machines as my filter is not defined, but I need some help from a fresh set of eyes.
I used 'else if' instead of 'elsif' and it didn't compile.
filter0: filter_memory generic map(n=>n) but your component name is filter_rom
try
filter0: filter_rom generic map(n=>n)
If you changed else if to elsif change it here also.
It compiles in Vivado 2017.4
Related
Here is my code for paralel in serial out shif register. I get error Near text "process"; expecting "if" and i cant fix this.
Here is my code
library ieee;
use ieee.std_logic_1164.all;
entity shiftreg is
port(
sl:in std_logic;
clk:in std_logic;
data:in std_logic_vector(3 downto 0);
q:out std_logic
);
end shiftreg;
architecture myarch of shiftreg is
signal q1:std_logic_vector(3 downto 0);
begin
process(sl,clk,data)
begin
if(sl='0') then
q1<=data;
else if(sl='1' and rising_edge(clk)) then
q<=q1(3);
q1(3)<=q1(2);
q1(2)<=q1(1);
q1(1)<=q1(0);
q1(0)<="0";
end if;
end process;
end myarch;
I'm currently programming a system in VHDL, and I'm using an enumerator from another package called vnir, which is defined as such:
package vnir is
type row_type_t is (ROW_NONE, ROW_NIR, ROW_BLUE, ROW_RED);
end package vnir;
I've defined my architecture as such
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vnir;
entity imaging_buffer is
port(
clock : in std_logic;
reset_n : in std_logic;
vnir_row_ready : in vnir.row_type_t
);
end entity imaging_buffer;
architecture rtl of imaging_buffer is
signal vnir_row_ready_i : vnir.row_type_t;
begin
vnir_pipeline : process (reset_n, clock) is
begin
if (reset_n = '0') then
vnir_row_ready_i <= vnir.ROW_NONE;
elsif rising_edge(clock) then
if (vnir_row_ready /= vnir.ROW_NONE) then
--do stuff
end if;
end if;
end process vnir_pipeline;
end architecture;
The internal signal vnir_row_ready_i can be assigned to no problem, however the relational operator doesn't seem to work as ModelSim throws this error when I try to compile:
# ** Error: C:/Users/nashg/Documents/iris_project/ex2_iris/vhdl/subsystems/sdram/Imaging Buffer/test.vhd(23): (vcom-1581) No feasible entries for infix operator '/='.
# ** Error: C:/Users/nashg/Documents/iris_project/ex2_iris/vhdl/subsystems/sdram/Imaging Buffer/test.vhd(23): Type error resolving infix expression "/=" as type std.STANDARD.BOOLEAN.
# ** Error: C:/Users/nashg/Documents/iris_project/ex2_iris/vhdl/subsystems/sdram/Imaging Buffer/test.vhd(28): VHDL Compiler exiting
My coworker helped me figure out how to make it work! I think that the /= operator is created in the vnir scope, but not ported over to the entity I'm working on. By writing :use work.vnir."/="; at the beginning of the file it compiles, so the full entity looks like so:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vnir;
use work.vnir."/=";
entity imaging_buffer is
port(
clock : in std_logic;
reset_n : in std_logic;
vnir_row_ready : in vnir.row_type_t
);
end entity imaging_buffer;
architecture rtl of imaging_buffer is
signal vnir_row_ready_i : vnir.row_type_t;
begin
vnir_pipeline : process (reset_n, clock) is
begin
if (reset_n = '0') then
vnir_row_ready_i <= vnir.ROW_NONE;
elsif rising_edge(clock) then
if (vnir_row_ready /= vnir.ROW_NONE) then
--do stuff
end if;
end if;
end process vnir_pipeline;
end architecture;
Alternatively it did work by including use work.vnir.all; and taking out the vnir. before the types, but that wasn't possible with the project I'm working one
Trying to make a UART Transmitter to send a data from FPGA to PC; 9600 baudrate, 8-bits, no parity, 1 start & stop bit; I wrote a code with VHDL, run synthesis and simulate it in a way I like it to be. I wanted to see it with BASYS 3 FPGA, After created constraints, Run Implementation issued an error in which its called "Opt_Design Error".
library ieee;
use ieee.std_logic_1164.all;
entity rs232_omo is
generic(clk_max:integer:=10400); --for baudrate
port(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
input : in std_logic_vector(7 downto 0);
done : out std_logic;
output : out std_logic;
showstates: out std_logic_vector(3 downto 0)
);
end entity;
architecture dataflow of rs232_omo is
type states is (idle_state,start_state,send_state,stop_state);
signal present_state,next_state : states;
signal data,data_next : std_logic;
begin
process(clk,rst)
variable count : integer range 0 to clk_max;
variable index : integer range 0 to 10;
begin
if rst='1' then
present_state<=idle_state;
count:=0;
data<='1';
done<='0';
elsif rising_edge(clk) then
present_state<=next_state;
count:=count+1;
index:=index+1;
data<=data_next;
end if;
end process;
process(present_state,data,clk,rst,start)
variable count : integer range 0 to clk_max;
variable index : integer range 0 to 10;
begin
done<='0';
data_next<='1';
case present_state is
when idle_state =>
showstates<="1000";
data_next<='1';
if start='1' and rst='0' then
count:=count+1;
if count=clk_max then
next_state<=start_state;
count:=0;
end if;
end if;
when start_state =>
showstates<="0100";
data_next<='0';
count:=count+1;
if count=clk_max then
next_state<=send_state;
count:=0;
end if;
when send_state =>
showstates<="0010";
count:=count+1;
data_next<=input(index);
if count=clk_max then
if index=7 then
index:=0;
next_state<=stop_state;
else
index:=index+1;
end if;
count:=0;
end if;
when stop_state =>
showstates<="0001";
count:=count+1;
if count=clk_max then
next_state<=idle_state;
done<='1';
count:=0;
end if;
end case;
end process;
output<=data;
end architecture;
This's the error message in detail
"[DRC MDRV-1]Multiple Driver Nets:Net done_OBUF has multiple drivers:
done_OBUF_inst_i_1/O,and done_reg/Q"
"[Vivado_Tcl 4-78] Error(s) found during DRC. Opt_Design not run."
What would be the reason for this error?
You are assigning done both in the first and the second process, which is exactly what the implementation is complaining about, you cannot have multiple drivers.
Remove done<='0'; from the first process and it should complete the implementation.
(I didn't check if the rest of the code is doing exactly what you want.)
I need to check my device wrapper logic, and one of the issue that I have is that IBUFDS instance not simulating correctly. I written simple test to check and to show what I mean.
Device.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Device is
Port (
CLK_P: in std_logic;
CLK_N: in std_logic;
CLK: out std_logic
);
end Device;
architecture arch of Device is
component IBUFDS
port (
O: out std_logic;
I: in std_logic;
IB: in std_logic
);
end component;
begin
D: IBUFDS
port map (
O => CLK,
I => CLK_P,
IB => CLK_N
);
end arch;
Device_tb.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Device_tb is
-- Port ( );
end Device_tb;
architecture Behavioral of Device_tb is
signal CLK, CLK_P, CLK_N: std_logic := '0';
begin
DEV: entity work.Device(arch)
port map(
CLK => CLK,
CLK_P => CLK_P,
CLK_N => CLK_N
);
CLK_gen: process
begin
CLK_P <= not CLK_P;
CLK_N <= CLK_P;
wait for 5 ns;
end process;
end Behavioral;
And the resulting simulation is
As you can see CLK out is always undefined. Don't know how to solve this, and is it solvable at all. I already thought about to architectures of my wrapper, but don't like this soulution, and maybe there are some better way to simulate this this. I tried to write generic map for IBUFDS instance but, elaborating step failing with error, that generic parameters not defined for IBUFDS.
I found this code which is a part of Exponentiation implementation, I believe this code is for parallel load register, the code had many mistakes, yet I tried to fix it and simplify it(simplification is to make it work), the original code is:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity REG is --Register entity
Port ( CLK,set,reset,In_LOAD : in std_logic;
Din_p: in std_logic_vector(m-1 to 0);
Din_s: in std_logic;
Dout: out std_logic);
end REG;
architecture behavior of REG is
signal Q_temp: std_logic_vector(m-1 down to 0);
begin
Dout<=”0”;
comb:process(In_LOAD,Din_s)
begin
if(In_LOAD=”1”) then Q_temp<=Din_p;end if;
end process comb;
state: process(CLK,set,reset)
begin
if(reset=”1”) then Q_temp<=(others=>”0”);end if;
if(set=”1”) then Q_temp<= (others=>”1”);
elsif(CLK’event and CLK=”1”) then
Q_temp:=Din_p & Q_temp(m-1 down to 1);
end if;
Dout<= Q_temp(0);
end process state;
end behavior;
while the code I modified is:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity REG2 is --Register entity
generic (m: integer := 4);
Port ( CLK,In_LOAD : in std_logic;
Din_p: in std_logic_vector(m-1 to 0);
Dout: out std_logic);
end REG2;
architecture behavior of REG2 is
signal Q_temp: std_logic_vector(m-1 downto 0);
begin
Dout<='0';
process(In_LOAD, Din_p, CLK)
begin
if (CLK'event and CLK='1') then
Q_temp <=Din_p;
elsif (In_LOAD='1') then
Q_temp <= Din_p & Q_temp(m-1 downto 1);
end if;
end process;
Dout <= Q_temp(0);
end behavior;
so my questions are : 1- why I'm getting this error :(Error (10344): VHDL expression error at REG2.vhd(18): expression has 0 elements, but must have 4 elements)?
2- this is a code for parallel load register, right?
thx
Plenty of things are wrong with your code (and the original code).
use the correct quote character " for bit strings and ' for bits instead of ”
downto is one word, not down to
m is not declared; perhaps this is supposed to be a generic?
Assign to Q_temp using signal assignment <= instead of variable assignment :=
Sensitivity lists for both your processes are incomplete
As #Morten mentions: the direction of Din_p should probably downto instead of to
Bonus (pet peeve): don't use IEEE.STD_LOGIC_ARITH and IEEE.STD_LOGIC_UNSIGNED, because they are not properly standardized. Use ieee.numeric_std instead.