Here is my code for paralel in serial out shif register. I get error Near text "process"; expecting "if" and i cant fix this.
Here is my code
library ieee;
use ieee.std_logic_1164.all;
entity shiftreg is
port(
sl:in std_logic;
clk:in std_logic;
data:in std_logic_vector(3 downto 0);
q:out std_logic
);
end shiftreg;
architecture myarch of shiftreg is
signal q1:std_logic_vector(3 downto 0);
begin
process(sl,clk,data)
begin
if(sl='0') then
q1<=data;
else if(sl='1' and rising_edge(clk)) then
q<=q1(3);
q1(3)<=q1(2);
q1(2)<=q1(1);
q1(1)<=q1(0);
q1(0)<="0";
end if;
end process;
end myarch;
Related
I want use internal signal of tag_mem entity in vivado in Test Bench.
Line with error in TB_tag_mem.vhd:
alias chTagMem is << signal .tag_mem.chTagMem : chTagMem_line >>;
Signal in tag_mem (tag_mem.vhd):
type chTagMem_line is array (natural range <>) of std_logic_vector (TAG_WIDTH downto 0);
signal chTagMem : chTagMem_line(CHAN_CNT - 1 downto 0);
When I run simulation, I see error in elaborate.log:
Starting static elaboration
ERROR: [VRFC 10-3763] type error near 'chtagmem' ; expected type 'chtagmem_line' [C:/Users/Mixen/CBDD/tag_mem/tag_mem.srcs/sim_1/new/TB_tag_mem.vhd:68]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit tb_tag_mem in library work failed.
How fix this?
Reproduce
TB_tag_mem.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.NUMERIC_STD.all;
entity TB_tag_mem is
-- Port ( );
end TB_tag_mem;
architecture Test of TB_tag_mem is
component tag_mem is
Port (
clk : in STD_LOGIC
);
end component;
-- for check
type chTagMem_line is array (natural range <>) of std_logic_vector (5 downto 0);
alias chTagMem is << signal .tag_mem.chTagMem : chTagMem_line >>;
begin
sim: process begin
report "TEST: Init";
wait;
end process sim;
end Test;
tag_mem.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity tag_mem is
Generic (
WIDTH: integer := 5
);
Port (
clk : in STD_LOGIC
);
end tag_mem;
architecture Behavioral of tag_mem is
type chTagMem_line is array (natural range <>) of std_logic_vector (WIDTH downto 0);
signal chTagMem : chTagMem_line(4 downto 0);
begin
end Behavioral;
I've created the following fsm to control a fir filter but I'm getting two errors while compiling.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
entity fsm is
generic (n: integer:=4);
port( clk: in STD_LOGIC;
rst: in STD_LOGIC;
a: out STD_LOGIC_VECTOR(2*n-1 downto 0));
end fsm;
architecture fsm_struct of fsm is
type state_type is (state0, state1, state2);
signal state: state_type;
signal rstff, rom_enable, ram_read_enable, ram_write_enable: STD_LOGIC;
component filter_rom is
generic (n: integer);
port ( clk: in STD_LOGIC;
rstff: in STD_LOGIC;
rom_enable : in STD_LOGIC;
ram_read_enable : in STD_LOGIC;
ram_write_enable : in STD_LOGIC;
a: out STD_LOGIC_VECTOR(2*n-1 downto 0));
end component;
begin
process(clk,rst)
variable delay1:integer:=0;
variable delay2:integer:=0;
variable delay3:integer:=0;
begin
if rst='1' then
state<=state0;
else if rising_edge(clk) then
case state is
when state0 => --initialize & input data
rom_enable<='1';
rstff<='1';
if delay1=1 then
rstff<='0';
state<=state1;
delay2:=0;
else
delay1:=delay1+1;
state<=state0;
end if;
when state1 => --write data to ram
if delay2=2 then
ram_write_enable<='1';
state<=state2;
delay3:=0;
else
delay2:=delay2+1;
state<=state1;
end if;
when state2 => --read data from ram
if delay3=1 then
ram_read_enable<='1';
state<=state0;
delay1:=0;
else
delay3:=delay3+1;
state<=state2;
end if;
end case;
end if;
end process;
filter0: filter_memory generic map(n=>n) port map(clk,rstff,rom_enable,ram_read_enable,ram_write_enable,a);
end fsm_struct;
The errors I'm getting are: Line 83: Syntax error near "process",
Line 85: Syntax error near "generic". at the end of the program. I know that my code won't even compile to any of your machines as my filter is not defined, but I need some help from a fresh set of eyes.
I used 'else if' instead of 'elsif' and it didn't compile.
filter0: filter_memory generic map(n=>n) but your component name is filter_rom
try
filter0: filter_rom generic map(n=>n)
If you changed else if to elsif change it here also.
It compiles in Vivado 2017.4
this is the code and saved it as IR.vhd, while the name of the project is saved as "8051"
when i try to compile a vhdl program in altera it is showing "Error (12007): Top-level design entity "8051" is undefined
" ... what does it mean ?
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity IR is
port(clk,rst,pb1:in std_logic;
irreg:in std_logic_vector(15 downto 0);
ops:out std_logic_vector(2 downto 0);
modes:out std_logic;
loc1:out std_logic_vector(3 downto 0);
loc2ordata:out std_logic_vector(7 downto 0));
end IR;
architecture rtl of IR is
signal ireg: std_logic_vector(15 downto 0);
begin
process (pb1)
begin
if(pb1='0')then --I am going to set up to feed in one instruction at a time
ireg<=irreg; --the instruction is executed when pb1 is pressed
end if;
end process;
ops<=ireg(15 downto 13);
modes<=ireg(12);
loc1<=ireg(11 downto 8);
loc2ordata<=ireg(7 downto 0);
end rtl;
Something I have noticed is that the top level entity name needs to be the same as the file name and module name. So if you called the top level IR, the file probably needs to be IR.v. Now I never capitalize my file names so I don't actually know if capitalization matching is important.
I have the following VHDL code, its a entity of a project:
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.typedef.all;
entity uc is
port(faaaa: in std_logic_vector(15 downto 0);
phi: in std_logic;
isDirect,isRam,jmp,store,NarOut,arpOut:out std_logic);
end entity uc;
architecture b8 of ua is
signal instt : std_logic_vector(15 downto 0);
signal bit7: std_logic;
begin
bit7<='0';
instt <= faaaa;
....
process(phi) is
....
end process;
end architecture b8;
The error says that:
object "faaaa" is used but not declared
What am I doing wrong here?
Your entity is called uc, but the architecture b8 is of ua.
I found this code which is a part of Exponentiation implementation, I believe this code is for parallel load register, the code had many mistakes, yet I tried to fix it and simplify it(simplification is to make it work), the original code is:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity REG is --Register entity
Port ( CLK,set,reset,In_LOAD : in std_logic;
Din_p: in std_logic_vector(m-1 to 0);
Din_s: in std_logic;
Dout: out std_logic);
end REG;
architecture behavior of REG is
signal Q_temp: std_logic_vector(m-1 down to 0);
begin
Dout<=”0”;
comb:process(In_LOAD,Din_s)
begin
if(In_LOAD=”1”) then Q_temp<=Din_p;end if;
end process comb;
state: process(CLK,set,reset)
begin
if(reset=”1”) then Q_temp<=(others=>”0”);end if;
if(set=”1”) then Q_temp<= (others=>”1”);
elsif(CLK’event and CLK=”1”) then
Q_temp:=Din_p & Q_temp(m-1 down to 1);
end if;
Dout<= Q_temp(0);
end process state;
end behavior;
while the code I modified is:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity REG2 is --Register entity
generic (m: integer := 4);
Port ( CLK,In_LOAD : in std_logic;
Din_p: in std_logic_vector(m-1 to 0);
Dout: out std_logic);
end REG2;
architecture behavior of REG2 is
signal Q_temp: std_logic_vector(m-1 downto 0);
begin
Dout<='0';
process(In_LOAD, Din_p, CLK)
begin
if (CLK'event and CLK='1') then
Q_temp <=Din_p;
elsif (In_LOAD='1') then
Q_temp <= Din_p & Q_temp(m-1 downto 1);
end if;
end process;
Dout <= Q_temp(0);
end behavior;
so my questions are : 1- why I'm getting this error :(Error (10344): VHDL expression error at REG2.vhd(18): expression has 0 elements, but must have 4 elements)?
2- this is a code for parallel load register, right?
thx
Plenty of things are wrong with your code (and the original code).
use the correct quote character " for bit strings and ' for bits instead of ”
downto is one word, not down to
m is not declared; perhaps this is supposed to be a generic?
Assign to Q_temp using signal assignment <= instead of variable assignment :=
Sensitivity lists for both your processes are incomplete
As #Morten mentions: the direction of Din_p should probably downto instead of to
Bonus (pet peeve): don't use IEEE.STD_LOGIC_ARITH and IEEE.STD_LOGIC_UNSIGNED, because they are not properly standardized. Use ieee.numeric_std instead.