I try to then execute exact same compilation command for that skipped file and it is being correctly compiled. But when I put it in make file it is just skipped. Every other file is generated.
Without actually seeing the makefile (which you haven't provided), we can only guess (though I'd like to think it's an educated guess).
Since make works by checking file timestamps to see if they need rebuilding, that's one thing to look at. If the timestamp of a target is later than that of all dependencies, the target won't be built.
The other is to ensure your top level rule actually has a dependency on what you're trying to build, somewhere in the hierarchy. By that I mean the ruleset:
all: xyzzy
xyzzy:
touch xyzzy
plugh:
touch plugh
with the command make all will never touch plugh because it's not in the dependency hierarchy off all.
And make generally provides command line options for debugging (like the -d flag in GNU Make) which will tell you why it's making the decisions it's making. If you want to understand what's happening, you should probably use them,a s it makes it that much easier to debug your makefile.
Related
I tried to use a make file in code::blocks but I am doing it wrong. I have the version installed with the compilers included. http://sourceforge.net/projects/codeblocks/files/Binaries/10.05/Windows/codeblocks-10.05mingw-setup.exe/download. What do I do with the make file? It starts with:
CC=gcc
best, US
You don't tend to execute the make file itself, rather you execute make, giving it the make file as an argument:
make -f pax.mk
If your make file is actually one of the standard names (like makefile or Makefile), you don't even need to specify it. It'll be picked up by default (if you have more than one of these standard names in your build directory, you better look up the make man page to see which takes precedence).
As paxdiablo said make -f pax.mk would execute the pax.mk makefile, if you directly execute it by typing ./pax.mk, then you would get syntax error.
Also you can just type make if your file name is makefile/Makefile.
Suppose you have two files named makefile and Makefile in the same directory then makefile is executed if make alone is given. You can even pass arguments to makefile.
Check out more about makefile at this Tutorial : Basic understanding of Makefile
I want to add a new fortran module into an existing fortran90 program. The existing fortran90 program is compiled by firstly running ./configure, then run the make and make install. If I want to define my own innovation, what else I need to do is export VER_USER=xxx, then make user and make installuser. It seems that make does the compilation job and make install does the installation job. And I need to add something like gfortran -o using_FKB using_FKB.o other.o ... -L/path_of_lib -lnewlib or path/to/libneural.a. So I need to debug the original Makefile. But I found it's difficult because the original Makefile is too long. I tried to use make -V=1 or make -d, and also make SHELL='sh -x' , but they prints so much things on my terminal...I could hardly debug. Is there anyway to debug it step by step?
By the way, there are too much $() variable in the Makefile. When I use ``make -V=1ormake -d, and also make SHELL='sh -x' , I found they hardly print the command in Makefilelike$(OBJ_PATH)=/path/obj_path...and it's quite hard for me to debug this...so is there any way to debug the Makefile``` step by step? Thanks!
I want to force a recipe for "output.file", even though it is up-to-date.
I have already tried make --assume-old=output.file output.file, but it does not run the recipe again.
In case you are curious: use case:
I want to use this together with --dry-run to find out the command that produce a target.
I ended up hiding the file to run make --dry-run output.file, but I was hoping for something more elegant + FMI: for future debugging makefile.
I think you're misunderstanding what that option does: it does exactly the opposite of what you hoped; from the man page:
-o file, --old-file=file, --assume-old=file
Do not remake the file file even if it is older than its dependen‐
cies, and do not remake anything on account of changes in file.
Essentially the file is treated as very old and its rules are
ignored.
You want output.file to be remade, so using -o is clearly not what you want.
There is no option in GNU make to say "always rebuild this target". What you can do is tell make to pretend that some prerequisite of the target you want to be rebuilt has been updated. See this option:
-W file, --what-if=file, --new-file=file, --assume-new=file
Pretend that the target file has just been modified. When used
with the -n flag, this shows you what would happen if you were to
modify that file. Without -n, it is almost the same as running a
touch command on the given file before running make, except that
the modification time is changed only in the imagination of make.
Say for example your output.file had a prerequisite input.file. Then if you run:
make -W input.file
it will show you what rules it would run, which would include rebuilding output.file.
I'd like to simplify the workflow so that rather than issuing these commands
$ make program_unittest
... output of $MAKE ...
$ ./program_unittest args
I could have my program automatically attempt to compile itself (if the source has been updated) when it is run, so that I do not have to go back and run make myself.
Here's what I'm thinking: My unit test build should first check if there is a makefile in the directory it's in, and if so, fork and exec make with the target corresponding to itself. If make determines "nothing to be done", it will continue on its way (running the unit-tests). However, if make actually performs a compilation, one of two things may happen. gcc (invoked by make) might be able to overwrite the build (an older version of which is already running) during compilation, in which case I can then perhaps exec it. If my system does not permit gcc to overwrite the program which is in use, then I have to quit the program before running make.
So this has become quite involved already. Are there perhaps more elegant solutions? Maybe I could use a bash script? How do I ascertain if make issued compilation commands or not?
Why not have make run the unit tests?
I have a tricky issue with gmake, when I build from the parent directory, something is different and the make does not build all the .o(s) it needs and fails, but if I cd to the directory and do a make it builds them fine.
How can I get GNUmake to tell me the difference between these two runs? There must be some make variables set in the parent that break the child, but I need help figuring out how to track them down.
If running make from the parent directory fails to build foo.o, then try make foo.o. If that fails then try running make -n foo.o in both directories (to print the commands instead of executing them) to see what it's doing differently. If it succeeds, then it's not even trying to build foo.o when run from the parent directory; make -n may shed some light, and as a last resort make -d will give you a torrent of information about the decision process, why it's doing what it's doing.
Here's a handy trick to see the value of variables. Put this rule in your makefile:
show_%:
#echo $# is $($*)
Now you can run make show_FOO and it will tell you the value of the variable FOO.
Finally, are you sure you know where you build your .o files? Make is very good at using things there to build files here, but not the other way around, so it can lose track of intermediate files if you're not careful.