I want to add a new fortran module into an existing fortran90 program. The existing fortran90 program is compiled by firstly running ./configure, then run the make and make install. If I want to define my own innovation, what else I need to do is export VER_USER=xxx, then make user and make installuser. It seems that make does the compilation job and make install does the installation job. And I need to add something like gfortran -o using_FKB using_FKB.o other.o ... -L/path_of_lib -lnewlib or path/to/libneural.a. So I need to debug the original Makefile. But I found it's difficult because the original Makefile is too long. I tried to use make -V=1 or make -d, and also make SHELL='sh -x' , but they prints so much things on my terminal...I could hardly debug. Is there anyway to debug it step by step?
By the way, there are too much $() variable in the Makefile. When I use ``make -V=1ormake -d, and also make SHELL='sh -x' , I found they hardly print the command in Makefilelike$(OBJ_PATH)=/path/obj_path...and it's quite hard for me to debug this...so is there any way to debug the Makefile``` step by step? Thanks!
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I tried to use a make file in code::blocks but I am doing it wrong. I have the version installed with the compilers included. http://sourceforge.net/projects/codeblocks/files/Binaries/10.05/Windows/codeblocks-10.05mingw-setup.exe/download. What do I do with the make file? It starts with:
CC=gcc
best, US
You don't tend to execute the make file itself, rather you execute make, giving it the make file as an argument:
make -f pax.mk
If your make file is actually one of the standard names (like makefile or Makefile), you don't even need to specify it. It'll be picked up by default (if you have more than one of these standard names in your build directory, you better look up the make man page to see which takes precedence).
As paxdiablo said make -f pax.mk would execute the pax.mk makefile, if you directly execute it by typing ./pax.mk, then you would get syntax error.
Also you can just type make if your file name is makefile/Makefile.
Suppose you have two files named makefile and Makefile in the same directory then makefile is executed if make alone is given. You can even pass arguments to makefile.
Check out more about makefile at this Tutorial : Basic understanding of Makefile
GNU make version 3.81, when I tab make -j20, there are so many errors and warnings. But when tab "make", then it will seccess ? Is there any relation with include "../build/Generic.mak"?
or when make -j20 will failed?
Sounds like your Makefile is simply not thread safe. That's why it doesn't work with -j parameter. The -j option tells make to run in parallel.
Unfortunately, the Makefile language is too complex to know exactly what is wrong with your build with the information you've given. It's a rather involved subject but you could try to read (a lot) about GNU make and automake to find some insight.
I try to then execute exact same compilation command for that skipped file and it is being correctly compiled. But when I put it in make file it is just skipped. Every other file is generated.
Without actually seeing the makefile (which you haven't provided), we can only guess (though I'd like to think it's an educated guess).
Since make works by checking file timestamps to see if they need rebuilding, that's one thing to look at. If the timestamp of a target is later than that of all dependencies, the target won't be built.
The other is to ensure your top level rule actually has a dependency on what you're trying to build, somewhere in the hierarchy. By that I mean the ruleset:
all: xyzzy
xyzzy:
touch xyzzy
plugh:
touch plugh
with the command make all will never touch plugh because it's not in the dependency hierarchy off all.
And make generally provides command line options for debugging (like the -d flag in GNU Make) which will tell you why it's making the decisions it's making. If you want to understand what's happening, you should probably use them,a s it makes it that much easier to debug your makefile.
I'd like to simplify the workflow so that rather than issuing these commands
$ make program_unittest
... output of $MAKE ...
$ ./program_unittest args
I could have my program automatically attempt to compile itself (if the source has been updated) when it is run, so that I do not have to go back and run make myself.
Here's what I'm thinking: My unit test build should first check if there is a makefile in the directory it's in, and if so, fork and exec make with the target corresponding to itself. If make determines "nothing to be done", it will continue on its way (running the unit-tests). However, if make actually performs a compilation, one of two things may happen. gcc (invoked by make) might be able to overwrite the build (an older version of which is already running) during compilation, in which case I can then perhaps exec it. If my system does not permit gcc to overwrite the program which is in use, then I have to quit the program before running make.
So this has become quite involved already. Are there perhaps more elegant solutions? Maybe I could use a bash script? How do I ascertain if make issued compilation commands or not?
Why not have make run the unit tests?
I am absolutely new in gfortran+minGW.
I need to create makefile.
When I run
$ gfortran -c q.f
All is ok!
But how can I run makefile like this?
CC = gfortran
q.o : q.f
$(CC) -c q2.o q2.f
I receive error “CC: command not found”.
(OS – Win 7 (64))
Tanks!!!
It kind of looks like you're trying to run the makefile as a regular script. Try
$ make
or
$ make -f mymakefilename
if you named the file something other than "makefile" or "Makefile".
You can potentially just execute the makefile, but if so you need a "shebang" line, something like
#!/usr/bin/make
at the top of the file, but frankly hardly anyone uses that option. Just use the make(1) command.
Update
It's because they're in the wrong order. Makefiles process (by default) the first target in the file. When you run make it sees the rule to make, q.o from q.f, it compiles it, and says, "Okay, I'm done."
If you put the q.exe target first, it says "Hmmm, I want to build q.exe and to do that I need a q.o. Do I have a q.o? No? Okay, hen I'll build a q.o. I have a rule for that -- I can build a q.o from q.f. okay, that's done. Now can I build q.exe? Oh, yes, I can. I'll build q.exe. Anything? Nope, I'm done."
If you were to use the commend
$ make q.exe
then you'd explicitly tell make to make q.exe, which would cause the same thing to happen, but better you should reorder your makefile and get used to the way they work.