I am designing a 2s complement code but it is showing that error can any one help me with that.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity comp is
port(a : in std_logic_vector(7 downto 0);
y : out std_logic_vector(7 downto 0));
end comp;
architecture dataflow of comp is
signal temp: std_logic;
begin
y<= not(a) + "00000001";
end dataflow;
Error: D:/modelsim_projects/2scmpliment.vhd(13): No feasible entries
for infix operator "+".
When using Synopsys packages, you need to add use of the std_logic_unsigned package after std_logic_1164, like:
use IEEE.std_logic_unsigned.all;
With this you can even use integer notation for addition like:
y <= not(a) + 1;
Alternative is to use the IEEE VHDL standard numeric_std package, with changes like:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
...
y <= std_logic_vector(unsigned(not(a)) + 1);
Related
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.std_logic_arith.ALL;
ENTITY mult4 IS
PORT (
a, b : IN std_logic_vector(3 DOWNTO 0);
cout : OUT std_logic_vector(7 DOWNTO 0)
);
END mult4;
ARCHITECTURE behave OF mult4 IS
SIGNAL result : std_logic_vector(7 DOWNTO 0);
BEGIN
arith_process : PROCESS (a, b)
VARIABLE p : INTEGER RANGE 0 TO 255;
BEGIN
p := TO_INTEGER(TO_unsigned ('0' & a)) * TO_INTEGER(TO_unsigned ('0' & b));
result <= TO_STDLOGICVECTOR(p, 8);
END PROCESS arith_process;
cout <= result;
END behave;
I'm still trying to fix the part of the to_integer, it's giving these errors now:
Error (10327): VHDL error at mult4.vhd(21): can't determine definition of operator ""&"" -- found 0 possible definitions
Error (10346): VHDL error at mult4.vhd(21): formal port or parameter "SIZE" must have actual or default value
Error (10784): HDL error at numeric_std_vhdl1993.vhd(712): see declaration for object "SIZE"
does anyone have any idea how to replace this part with something simpler?
I am new to vhdl, I am trying to add 2 vectors of 5 bit unsigned numbers.In the following code the signal firstsum gives proper output in waveform but the vector sum does not show any output, I am using quartus ii. What is the error in this code?
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package UVEC is
subtype UINT5 is std_logic_vector (4 downto 0);
type UVEC5 is array (2 downto 0) of UINT5;
subtype UINT6 is std_logic_vector (5 downto 0);
type UVEC6 is array (2 downto 0) of UINT6;
end UVEC;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.UVEC.all;
entity FP_Vecsum1 is
port(
a,b : in UVEC5;
sum : out UVEC6;
firstsum : out UINT6
);
end FP_Vecsum1;
architecture FP_Vecsum1_MX of FP_Vecsum1 is
begin
firstsum <= std_logic_vector(('0'&unsigned(a(0)))+('0'&unsigned(b(0))));
sum(0) <= std_logic_vector(('0'&unsigned(a(0)))+('0'&unsigned(b(0))));
sum(1) <= std_logic_vector(('0'&unsigned(a(1)))+('0'&unsigned(b(1))));
sum(2) <= std_logic_vector(('0'&unsigned(a(2)))+('0'&unsigned(b(2))));
end FP_Vecsum1_MX;
welcome to the VHDL world.
I also haven't found anything wrong with your code, but you can try the following, maybe this will help:
first, try to cast the signals to unsigned in the beginning of your architecture, before doing the math:
a_us(0) <= unsigned(a(0));
a_us(1) <= unsigned(a(1));
a_us(2) <= unsigned(a(2));
this is quite convenient: if your ports to the outside world are neutral vectors, the math inside your component is either signed or unsigned. do the conversion once, and you're free.
second, instead of manually doing the sign extension, now that you have determined your vectors as unsigned, you can use resize function to automatically set the summed vectors to the result length:
sum(0) <= std_logic_vector(resize(a_us(0),sum(0)'length) + resize(b_us(0),sum(0)'length));
you can also do a little trick by adding a zero with a relevant vector width:
sum(0) <= std_logic_vector( to_unsigned(0,sum(0)'length) + a_us(0) + b_us(0) );
it might look a little longer, but in my opinion it's a more robust code.
hope this helps,
ilan.
I have just started VHDL module in university and my lecturer isn't good a explaining things. How to I use/declare signed values in VHDL?
This is the basic code format I have been taught and I'm currently programming a 2bit subtractor. The information in other websites are quite confusing.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
entity TwoBitSubtractor is port(
x,y :in integer range 0 to 3;
result :out integer range 0 to 3);
end TwoBitSubtractor;
architecture gates of TwoBitSubtractor is
begin
result<= x - y;
end gates;
You should use signed type for specifying signed values. Integer can also be used to declare values in a more human readable manner, but with that you are out of bit-level definitions, which is not desired in VHDL in my opinion. For example, you are ignoring the the amount of bits used for any signal with integer, which can be good for a high level language, but not too useful for VHDL.
library ieee;
use ieee.numeric_std.all;
entity TwoBitSubtractor is port(
x : in signed(2 downto 0);
y : in signed(2 downto 0);
result : out signed(2 downto 0));
end TwoBitSubtractor;
architecture gates of TwoBitSubtractor is
begin
result <= x - y;
end gates;
See the way they are declared within the entity port. More details on signed/unsigned, please check here
Also a working online simulation of TwoBitSubtractor with testbench, check here
I had in mind to take modulo for fixed point numbers in VHDL and I'm using fixed point package, I ran into this:
ERROR:HDLParsers:808 - "F:/prj/ofdm/test2.vhd" Line 53. mod can not have such operands in this context.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use IEEE_PROPOSED.fixed_float_types.all;
-- Uncomment the following library declaration if using
use IEEE.numeric_STD.all;
use IEEE.std_logic_arith.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test2 is
port(
clk : in std_logic;
a1 : in std_logic_vector(11 downto 0);
--a2:in std_logic_vector(11 downto 0);
output : out std_logic_vector(17 downto 0)
);
end test2;
architecture Behavioral of test2 is
signal tmp : sfixed(3 downto -14) := "011001001000011111"; -- 4+12pi~=6.28314
begin
process(clk)
begin
output <= to_slv(to_sfixed(a1, 5, -6) mod tmp); --[4+14]
-- tmp <= signed(a1)*signed(a2)*a;
-- output <= std_logic_vector(tmp);
end process;
end Behavioral;
As the title say I need to write a vhdl code that take as input a 32 bit vector and a 6 bit vector. I need to output another 32 bit vector which is equal the input 32 bit vector but the nth bit of it is flipped. n= the number of the 6 bit vector. Here is my code but is incorrect.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity flipMSB is
Port ( Anotf : in STD_LOGIC_VECTOR (31 downto 0);
count : in STD_LOGIC_VECTOR (5 downto 0);
Af : out STD_LOGIC_VECTOR (31 downto 0));
end flipMSB;
architecture bhv of flipMSB is
signal sig: STD_LOGIC_VECTOR(31 downto 0);
signal n : integer;
begin
n<=CONV_INTEGER(count);
sig<=Anotf;
sig(n)<=not sig(n);
Af<=sig;
end bhv;
First, a 6 bit number goes up to 64, you only need 5 bits for your count signal!
Second:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
std_logic_arith and numeric_std have conflicting types. Since std_logic_arith and std_logic_unsigned are not part of the VHDL standard (and IEEE, despite the library name), I suggest you only use numeric_std. If you use VHDL-2008, you can use numeric_std_unsigned. You will need to replace n <= conv_integer(count) with n <= to_integer(unsigned(count))
Finally,
sig<=Anotf;
sig(n)<=not sig(n);
will have two output driver for the bit n, which is bad. If you put that logic into a process, it would be fine since the first assignation to sig(n) would be overridden (instead of driven twice):
process(Anotf, count)
variable n : natural;
begin
Af <= Anotf;
n := to_integer(unsigned(count));
Af(n) <= not Anotf(n);
end process;
Think of it this way, if two processes drive the same signal, this result in two drivers (and conflict!). A statement outside a process is implicitly in its own process. Also, in a process only the last statement assigning a signal will have an effect.