I had in mind to take modulo for fixed point numbers in VHDL and I'm using fixed point package, I ran into this:
ERROR:HDLParsers:808 - "F:/prj/ofdm/test2.vhd" Line 53. mod can not have such operands in this context.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use IEEE_PROPOSED.fixed_float_types.all;
-- Uncomment the following library declaration if using
use IEEE.numeric_STD.all;
use IEEE.std_logic_arith.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test2 is
port(
clk : in std_logic;
a1 : in std_logic_vector(11 downto 0);
--a2:in std_logic_vector(11 downto 0);
output : out std_logic_vector(17 downto 0)
);
end test2;
architecture Behavioral of test2 is
signal tmp : sfixed(3 downto -14) := "011001001000011111"; -- 4+12pi~=6.28314
begin
process(clk)
begin
output <= to_slv(to_sfixed(a1, 5, -6) mod tmp); --[4+14]
-- tmp <= signed(a1)*signed(a2)*a;
-- output <= std_logic_vector(tmp);
end process;
end Behavioral;
Related
I made a state automate for this diagram:
Diagram with states
(not a from diagram represents a='0' and b with horizontal bar above represents b='0')
And I write structural and comportamental automate, structural with mux4:1 and 3 d flip-flops.
I made a testbench file in which i give simulate values for a and b variables like this:
a<='0' after 2ns,'1' after 5ns,'0' after 8ns,'1' after 11ns,'1' after 16ns;--se va incepe dupa rn, dupa 2 ns
b<='1' after 11ns,'0' after 13ns;
, for clock:
process
begin
ck<='0';
wait for 0.5ns;
ck<='1';
wait for 0.5ns;
end process;
and for an asynchronous reset:
rn<='1' after 0ns,'0' after 0.2ns,'1' after 2ns;
with this rn i will be starting showing the states and giving a logic value for a and b only after 2 ns
Test result is wrong
The test shows the wrong states for structural description only for first scrolling, after that is equal to the comportamental description. How I can make to show all the curls for this diagram, not only this which is the complete?
I add there the vhdl code for structural and comportamental description, mux4, d flip-flop and test:
Structural:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity automat is
Port ( ck : in STD_LOGIC;
rn : in STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (2 downto 0));
end automat;
architecture structural of automat is
component mux4 is
Port ( a0 : in STD_LOGIC;
a1 : in STD_LOGIC;
i0 : in STD_LOGIC;
i1 : in STD_LOGIC;
i2 : in STD_LOGIC;
i3: in STD_LOGIC;
Y : out STD_LOGIC);
end component;
component dff is
Port ( d : in STD_LOGIC;
ck : in STD_LOGIC;
rn: in STD_LOGIC;
q : out STD_LOGIC;
qn : out STD_LOGIC);
end component;
signal q2,q1,q0,d2,d1,d0:std_logic;
signal an,bn,q0n:std_logic;
signal net1,net2:std_logic;
begin
q0n<=not q0;
q<=q2& q1& q0;
an<=not a;
bn<=not b;
--cele 5 muxuri necesare descrierii structurale
mux412:mux4 port map(i0=>'1',i1=>'0',i2=>'0',i3=>'0',a1=>q0,a0=>b,y=>net1);
mux41:mux4 port map(i0=>'0',i1=>a,i2=>'1',i3=>net1,a1=>q2,a0=>q1,y=>d2);
mux42:mux4 port map(i0=>'1',i1=>an,i2=>q0,i3=>q0n,a1=>q2,a0=>q1,y=>d1);
mux432: mux4 port map(i0=>'0',i1=>'1',i2=>'0',i3=>'0',a1=>q0,a0=>a,y=>net2);
mux43:mux4 port map(i0=>'1',i1=>an,i2=>net2,i3=>q0n,a1=>q2,a0=>q1,y=>d0);
--cele 3 bistabile d necesare
dff2:dff port map(d=>d2, ck=>ck, rn=>rn, q=>q2);
dff1:dff port map(d=>d1, ck=>ck, rn=>rn, q=>q1);
dff0:dff port map(d=>d0, ck=>ck, rn=>rn, q=>q0);
end architecture;
Mux4:1 :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--descriere multiplexor 4:1
entity mux4 is
Port ( a0 : in STD_LOGIC;
a1 : in STD_LOGIC;
i0 : in STD_LOGIC;
i1 : in STD_LOGIC;
i2 : in STD_LOGIC;
i3: in STD_LOGIC;
Y : out STD_LOGIC);
end mux4;
architecture Behavioral of mux4 is
signal A : STD_LOGIC_VECTOR(1 downto 0);
begin
--mux4: process (a1,a0,i0,i1,i2,i3)
--begin
A<=a1 & a0;
Y<=i0 when A="00"
else i1 when A="01"
else i2 when A="10"
else i3;
end Behavioral;
D Flip-Flop:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--descriere bistabil d
entity dff is
Port ( d : in STD_LOGIC;
ck : in STD_LOGIC;
rn: in STD_LOGIC;
q : out STD_LOGIC;
qn : out STD_LOGIC);
end dff;
architecture Behavioral of dff is
begin
flip_flop: process(ck,rn)
begin
if rn='0' then
q <= '0';
else
if rising_edge(ck) then
q <= d;
qn <= not d;
end if;
end if;
end process;
end Behavioral;
Comportamental:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity combinat is
Port ( ck : in STD_LOGIC;
rn : in STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (2 downto 0));
end combinat;
architecture Behavioral of combinat is
signal cur_poz,next_poz:std_logic_vector(2 downto 0);
begin
q<=cur_poz;
process(ck,rn)
begin
if rn='0' then
cur_poz<="000";
elsif rising_edge(ck) then
cur_poz<=next_poz;
end if;
end process;
process(cur_poz,a,b)
begin
case cur_poz is
when "000"=>next_poz<="011";
when "011"=>if a='1' then
next_poz<="100";
else
next_poz<="011";
end if;
when "100"=>if a='1' then
next_poz<="101";
else
next_poz<="100";
end if;
when "101"=>next_poz<="110";
when "110"=>if b='1' then
next_poz<="011";
else
next_poz<="111";
end if;
when "111"=>next_poz<="000";
when others=>next_poz<="000";
end case;
end process;
end Behavioral;
Testbench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test is
-- Port ( );
end test;
architecture Behavioral of test is
component automat is
Port ( ck : in STD_LOGIC;
rn : in STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (2 downto 0));
end component;
component combinat is
Port ( ck : in STD_LOGIC;
rn : in STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (2 downto 0));
end component;
signal ck,rn,a,b:std_logic;
signal qsec,qcomb:std_logic_vector(2 downto 0);
begin
Testare1: automat port map(ck=>ck,--pentru test descriere structurala
rn=>rn,
a=>a,
b=>b,
q=>qsec);
Testare2:combinat port map(ck=>ck,--pentru test descriere comportamentala
rn=>rn,
a=>a,
b=>b,
q=>qcomb);
rn<='1' after 0ns,'0' after 0.2ns,'1' after 2ns;
process
begin
ck<='0';
wait for 0.5ns;
ck<='1';
wait for 0.5ns;
end process;
a<='0' after 2ns,'1' after 5ns,'0' after 8ns,'1' after 11ns,'1' after 16ns;--se va incepe dupa rn, dupa 2 ns
--evaluarea timpilori si valorilor parametrilor conform buclelor din diagrama gasite
b<='1' after 11ns,'0' after 13ns;
--a<='0' after 2ns,'1' after 4ns,'0' after 6ns,'1' after 8ns,'0' after 16ns;
--b<='1' after 8ns,'0' after 10ns;
verificare:process(qsec)--verificare daca corespund rezultatele celor 2 structuri
begin
if qsec/=qcomb then
report "Rezultat al descrierii structurale diferit fata de cea comportamentale";
end if;
end process;
end Behavioral;
I have implemnted Carry Select Adder using D-lATCh. But I am Getting the following error.
HDLCompiler:720 - "/home/aabhinav/Downloads/Example/CSA_4bits/CSA_BEC1.vhd" Line 76: Positional association cannot follow named association
ERROR:HDLCompiler:854 - "/home/aabhinav/Downloads/Example/CSA_4bits/CSA_BEC1.vhd" Line 41: Unit ignored due to previous errors.
Below is my attached code. If anyone could help me as I am new to VHDL and doing my school project.
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:08:00 11/16/2016
-- Design Name:
-- Module Name: CSA_BEC1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CSA_BEC1 is
port( A,B : in std_logic_vector(3 downto 0);
cin : in std_logic;
Scsa : out std_logic_vector(4 downto 0));
end CSA_BEC1;
architecture Behavioral of CSA_BEC1 is
COMPONENT d_latch_top is
port( A : in std_logic_vector(4 downto 0);
EN : IN STD_LOGIC;
B : out std_logic_vector(4 downto 0));
end COMPONENT;
COMPONENT MUX10_5 is
PORT(X, Y: in std_logic_vector(4 downto 0);
sel: in std_logic;
m: out std_logic_vector(4 downto 0));
end COMPONENT;
component rc_adder
Port ( X : in STD_LOGIC_VECTOR (3 downto 0);
Y : in STD_LOGIC_VECTOR (3 downto 0);
-- Cin: in STD_LOGIC ;
sum : out STD_LOGIC_VECTOR (3 downto 0);
Carry : out STD_LOGIC);
end component;
signal RCSum: STD_LOGIC_VECTOR( 3 DOWNTO 0);
signal BECSum, M: STD_LOGIC_VECTOR( 4 DOWNTO 0);
signal RCCarry,BECCarry: STD_LOGIC;
signal RC_S_C: STD_LOGIC_VECTOR( 4 DOWNTO 0);
begin
RC: rc_adder PORT MAP(X => A, Y => B, SUM => RCSum, Carry => RCCarry);
RC_S_C <= RCCarry&RCSum;
dlatch: d_latch_top PORT MAP(A => RC_S_C,B => BECSum, EN = '1');
MUX: MUX10_5 PORT MAP(X => BECSum, y => RC_S_C , sel => cin, m => Scsa);
end Behavioral;
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:19:36 11/16/2016
-- Design Name:
-- Module Name: rc_adder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rc_adder is
port( X : in std_logic_vector(3 downto 0); --4 bit input 1
Y : in std_logic_vector(3 downto 0); -- 4 bit input 2
-- Cin : in STD_LOGIC;
sum : out std_logic_vector(3 downto 0); -- 4 bit sum
carry : out std_logic -- carry out.
);
end rc_adder;
architecture logic of rc_adder is
COMPONENT full_adder is
port (a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
carry : out std_logic
);
end COMPONENT;
signal C0: STD_LOGIC_VECTOR( 2 DOWNTO 0);
begin
FA1: full_adder PORT MAP(X(0),Y(0),'0',sum(0),C0(0));
FA2: full_adder PORT MAP(X(1),Y(1),C0(0),sum(1),C0(1));
FA3: full_adder PORT MAP(X(2),Y(2),C0(1),sum(2),C0(2));
FA4: full_adder PORT MAP(X(3),Y(3),C0(2),sum(3),Carry);
end logic;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity d_latch_top is
Port ( A : in std_logic_vector(4 downto 0);
EN : in STD_LOGIC;
B : out std_logic_vector(4 downto 0));
end d_latch_top;
architecture Behavioral of d_latch_top is
signal DATA : std_logic_vector(4 downto 0);
begin
DATA <= A when (EN = '1') else DATA;
B <= DATA;
end Behavioral;
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:54:06 11/12/2016
-- Design Name:
-- Module Name: MUX10_5 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUX10_5 is
PORT( X, Y: in std_logic_vector(4 downto 0);
sel: in std_logic;
m: out std_logic_vector(4 downto 0));
end MUX10_5;
architecture logic of MUX10_5 is
component MUX6_3 is
PORT( sel: in std_logic;
X, Y: in std_logic_vector(2 downto 0);
m: out std_logic_vector(2 downto 0));
end component;
component MUX4_2 is
PORT( sel, X0, X1, Y0, Y1: in std_logic;
m0, m1: out std_logic);
end component;
begin
mux6_3_inst0 : MUX6_3
PORT MAP( sel => sel, X => X(2 downto 0), Y => Y(2 downto 0),
m => m(2 downto 0));
mux4_2_inst0 : MUX4_2
PORT MAP( sel => sel, X0 => X(3), X1 => X(4), Y0 => Y(3), Y1 => Y(4),
m0 => m(3), m1 => m(4));
end logic;
See IEEE Std 1076-2008 6.5.7 Association lists, 6.5.7.1 General, para 5:
Named associations can be given in any order, but if both positional and named associations appear in the same association list, then all positional associations shall occur first at their normal position. Hence once a named association is used, the rest of the association list shall use only named associations.
In the architecture for CSA_BEC1, the component instantiation labeled dlatch, pretty much where the first error message said. The named association malformed: EN = '1' should be EN => '1'.
A VHDL parser can be implemented LALR(1), meaning it doesn't need to look ahead beyond the next token. You might imagine someone was using the compound delimiter "=>" to determine whether or not an association item is named or positional. It seems it's not smart enough to give a separate error message when the following delimiter ("="), wasn't a ',' or a ')' for the last item in an association list.
Such 'luxuries' usually show up with tool implementation maturity. Fee free to allow the vendor to know the error message is not particularly enlightening.
How to generate a PWM signal using an FPGA? Which is best method to generate a variable duty cycle?
I tried to solve this problem by using the following code but two or three errors occurred.
This is my code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
--use ieee.float_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pwm_sne is
Generic(
sys_clk :integer :=50000000;
pwm_freq :integer :=100000;
bits_resolution :integer :=8
);
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
k : in STD_LOGIC_VECTOR (7 downto 0);
y : out STD_LOGIC
);
end pwm_sne;
architecture Behavioral of pwm_sne is
signal cnt :std_logic_vector(7 downto 0);
signal flag :std_logic;
signal reg :std_logic_vector(7 downto 0);
--variable duty :std_logic:=0;
begin
process(clk,rst)
begin
if rst='1' then
cnt<="00000000";
elsif(clk'event and clk='1')then
cnt<=cnt+"00000001";
elsif cnt="11111111" then
flag<='0';
cnt<="00000000";
end if;
end process;
process(clk,flag)
begin
if(clk'event and clk='1') then
reg<=k;
end if;
end process;
process(cnt,reg)
begin
if(flag='0')then
elsif cnt>reg then
y<=(reg/256)*100;
--y<=duty;
elsif cnt=reg then
y<=(reg/256)*100;
elsif cnt<=reg then
y<=period;
--y<=duty;
end if;
end process;
end Behavioral;
The errors occurred in output value y and at the division operation.
Please suggest a good method to solve the problems from above.
Solution : Do maths on numbers, not on untyped bags of bits.
If cnt, reg,k were natural range 0 to 255 and you compared cnt with 0 or 255 and added 1 to it, this would just work. And if k MUST be std_logic_vector, use ONE type conversion function between it and reg.
Also recommended : delete the non-standard std_logic_arith andstd_logic_unsignedlibs and usenumeric_std` instead.
I am trying to add two std_logic_vectors using the notation given below:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.NUMERIC_STD.ALL;
entity adder is
port( a:in std_logic_vector(31 downto 0);
b:in std_logic_vector(31 downto 0);
o:out std_logic_vector(31 downto 0));
end adder;
architecture Behavioral of adder is
begin
o<=a+b;
end Behavioral;
One possibility is to generate the result with carry, and then split that afterwards, like:
architecture Behavioral of adder is
signal c_o : std_logic_vector(o'length downto 0); -- Result with carry
signal c : std_logic; -- Carry only
begin
c_o <= ('0' & a) + b; -- Result with carry; extended with '0' to keep carry
o <= c_o(o'range); -- Result without carry
c <= c_o(c_o'left); -- Carry only
end Behavioral;
You can do this. The carry is not saved, but it's being reported that there was an overflow.
function "+" (Add1: std_logic_vector; Add2: std_logic_vector) return std_logic_vector is
variable big_sum: bit_vector(Add1'LENGTH downto 0);
begin
big_sum = Add1 + Add2;
assert big_sum(Add1'LENGTH) = 0
report "overflow"
severity warning;
return big_sum(Add1'LENGTH-1 downto 0);
Of course you'll need to define a new package and also include that package in your already existing file.
o<=std_logic_vector(unsigned(a)+unsigned(b))
Although I suggest you use unsigned/signed on your ports (and have a clock cycle of latency).
If you want the carry
o_with_carry <= std_logic_vector('0'&unsigned(a)+unsigned(b));
o_carry <= o_with_carry(o_with_carry'high);
o <= o_with_carry(o'range);
I'm trying to create this code for a circuit, but it tells me there's an error.
The code is:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity seq is
port( CLK : in std_logic;
GEN : in std_logic;
INI : in std_logic;
B : in std_logic_vector(3 downto 0);
Qo : out std_logic_vector(3 downto 0)
);
end seq;
architecture behavior of seq is
signal Qo_pre: std_logic_vector(3 downto 0);
begin
process (GEN, INI, CLK, B)
begin
if INI='1' then
Qo <= B;
elsif (INI='0' and GEN='1' and rising_edge(CLK)) then
Qo(0)<= Qo_pre(1);
Qo(1)<= Qo_pre(2);
Qo(2)<= Qo_pre(3);
end if;
end process;
Qo(3)<= not Qo_pre(3) when (INI='0' and GEN='1' and rising_edge(CLK) and (Qo_pre(3) xnor Qo_pre(0))='1')
end behavior;
The error that appears is:
Line 51. parse error, unexpected IDENTIFIER
help please :(
You are missing a semicolon, on the assignment before end behavior;.
When I paste the code in my tool, it is on line 31.