Write code that flip the nth bit - vhdl

Question

As the title say I need to write a vhdl code that take as input a 32 bit vector and a 6 bit vector. I need to output another 32 bit vector which is equal the input 32 bit vector but the nth bit of it is flipped. n= the number of the 6 bit vector. Here is my code but is incorrect.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity flipMSB is
Port ( Anotf : in STD_LOGIC_VECTOR (31 downto 0);
count : in STD_LOGIC_VECTOR (5 downto 0);
Af : out STD_LOGIC_VECTOR (31 downto 0));
end flipMSB;
architecture bhv of flipMSB is
signal sig: STD_LOGIC_VECTOR(31 downto 0);
signal n : integer;
begin
n<=CONV_INTEGER(count);
sig<=Anotf;
sig(n)<=not sig(n);
Af<=sig;
end bhv;

Answer 1

First, a 6 bit number goes up to 64, you only need 5 bits for your count signal!
Second:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
std_logic_arith and numeric_std have conflicting types. Since std_logic_arith and std_logic_unsigned are not part of the VHDL standard (and IEEE, despite the library name), I suggest you only use numeric_std. If you use VHDL-2008, you can use numeric_std_unsigned. You will need to replace n <= conv_integer(count) with n <= to_integer(unsigned(count))
Finally,
sig<=Anotf;
sig(n)<=not sig(n);
will have two output driver for the bit n, which is bad. If you put that logic into a process, it would be fine since the first assignation to sig(n) would be overridden (instead of driven twice):
process(Anotf, count)
variable n : natural;
begin
Af <= Anotf;
n := to_integer(unsigned(count));
Af(n) <= not Anotf(n);
end process;
Think of it this way, if two processes drive the same signal, this result in two drivers (and conflict!). A statement outside a process is implicitly in its own process. Also, in a process only the last statement assigning a signal will have an effect.