How to generate a PWM signal using an FPGA? Which is best method to generate a variable duty cycle?
I tried to solve this problem by using the following code but two or three errors occurred.
This is my code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
--use ieee.float_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pwm_sne is
Generic(
sys_clk :integer :=50000000;
pwm_freq :integer :=100000;
bits_resolution :integer :=8
);
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
k : in STD_LOGIC_VECTOR (7 downto 0);
y : out STD_LOGIC
);
end pwm_sne;
architecture Behavioral of pwm_sne is
signal cnt :std_logic_vector(7 downto 0);
signal flag :std_logic;
signal reg :std_logic_vector(7 downto 0);
--variable duty :std_logic:=0;
begin
process(clk,rst)
begin
if rst='1' then
cnt<="00000000";
elsif(clk'event and clk='1')then
cnt<=cnt+"00000001";
elsif cnt="11111111" then
flag<='0';
cnt<="00000000";
end if;
end process;
process(clk,flag)
begin
if(clk'event and clk='1') then
reg<=k;
end if;
end process;
process(cnt,reg)
begin
if(flag='0')then
elsif cnt>reg then
y<=(reg/256)*100;
--y<=duty;
elsif cnt=reg then
y<=(reg/256)*100;
elsif cnt<=reg then
y<=period;
--y<=duty;
end if;
end process;
end Behavioral;
The errors occurred in output value y and at the division operation.
Please suggest a good method to solve the problems from above.
Solution : Do maths on numbers, not on untyped bags of bits.
If cnt, reg,k were natural range 0 to 255 and you compared cnt with 0 or 255 and added 1 to it, this would just work. And if k MUST be std_logic_vector, use ONE type conversion function between it and reg.
Also recommended : delete the non-standard std_logic_arith andstd_logic_unsignedlibs and usenumeric_std` instead.
Related
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fourToSixteenDecoder is
port ( a : in std_logic_vector(0 to 3);
EN : in STD_LOGIC;
Y : out std_logic_vector(0 to 15));
end fourToSixteenDecoder;
architecture Behavioral of fourToSixteenDecoder is
begin
process(a, EN)
variable inputs : integer := conv_integer(unsigned(a));
variable Y_c : std_logic_vector(0 to 15);
begin
Y_c := X"0000";
if (EN = '1') then
Y_c(inputs) := '1';
elsif (EN = '0') then
Y_c := X"0000";
end if;
Y <= Y_c;
end process;
end Behavioral;
Trying to make a 4-16 Decoder, however, I am trying to use conversion between integer and SLV to do bit indexing assignment, but the conversion does not work.
ERROR:HDLCompiler:806 - "..." Line 40: Syntax error near "b".
Also tried
to_integer(unsigned())
integer(unsigned())
integer(to_unsigned())
to_integer(to_unsigned())
use IEEE.ARITH and IEEE.STD_LOGIC.UNSIGNED
No solution.
The conversion routine is call to_integer in package numeric_std, and for an unsigned produces a natural range integer.
With variable inputs : integer := to_integer(unsigned(a)); inputs would be initialized to the initial value of a converted to an integer (likely 0 if a is uninitialized (all 'U's).
There is no other assignment to inputs and inputs wouldn't change with a value changes.
Replace the variable inputs declaration with
variable inputs: integer range 0 to 15;
which restricts the range of inputs to the index range of Y_c.
Add
inputs := to_integer(unsigned(a));
as a first sequential statement to the process.
The two assignments:
Y_c := X"0000";
are redundant. The elsif can be eliminated:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fourToSixteenDecoder is
port (
a: in std_logic_vector(0 to 3);
EN: in std_logic;
Y: out std_logic_vector(0 to 15)
);
end entity fourToSixteenDecoder;
architecture Behavioral of fourToSixteenDecoder is
begin
process(a, EN)
-- variable inputs : integer := conv_integer(unsigned(a));
variable inputs: integer range 0 to 15;
variable Y_c: std_logic_vector(0 to 15);
begin
inputs := to_integer(unsigned(a)); -- ADDED
Y_c := X"0000";
if EN = '1' then
Y_c(inputs) := '1';
-- elsif (EN = '0') then
-- Y_c := X"0000";
end if;
Y <= Y_c;
end process;
end architecture Behavioral;
This analyzes, elaborates and simulates. Notice the parentheses around the if statement conditions aren't needed.
A testbench:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_4to16 is
end entity;
architecture fum of tb_4to16 is
signal a: std_logic_vector (0 to 3) := (others => '0');
signal EN: std_logic;
signal Y: std_logic_vector(0 to 15);
begin
DUT:
entity work.fourtosixteendecoder
port map (
a => a,
EN => EN,
Y => Y
);
STIMULI:
process
begin
for i in 0 to 15 loop
EN <= '0';
a <= std_logic_vector(to_unsigned(i,4));
wait for 10 ns;
EN <='1';
wait for 10 ns;
end loop;
EN <= '0';
wait for 10 ns;
wait;
end process;
end architecture;
The results:
I had in mind to take modulo for fixed point numbers in VHDL and I'm using fixed point package, I ran into this:
ERROR:HDLParsers:808 - "F:/prj/ofdm/test2.vhd" Line 53. mod can not have such operands in this context.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use IEEE_PROPOSED.fixed_float_types.all;
-- Uncomment the following library declaration if using
use IEEE.numeric_STD.all;
use IEEE.std_logic_arith.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test2 is
port(
clk : in std_logic;
a1 : in std_logic_vector(11 downto 0);
--a2:in std_logic_vector(11 downto 0);
output : out std_logic_vector(17 downto 0)
);
end test2;
architecture Behavioral of test2 is
signal tmp : sfixed(3 downto -14) := "011001001000011111"; -- 4+12pi~=6.28314
begin
process(clk)
begin
output <= to_slv(to_sfixed(a1, 5, -6) mod tmp); --[4+14]
-- tmp <= signed(a1)*signed(a2)*a;
-- output <= std_logic_vector(tmp);
end process;
end Behavioral;
I'm trying to use RAM in order to read/write. My address is an integer value and it should be a memory of integers. This is my code below but i keep getting an error.
This is from my data path where the address selection is from a register of integers.
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Mem is
generic( width: integer:=4;
depth: integer:=4;
addr: integer:=2);
port( Clock: in std_logic;
Enable: in std_logic;
Read: in std_logic;
Write: in std_logic;
Read_Addr: in integer;
Write_Addr: in integer;
Data_in: in integer;
Data_out: out integer
);
end Mem;
--------------------------------------------------------------
architecture behav of Mem is
type ram_type is array (0 to 31) of
integer;
signal tmp_ram: ram_type;
begin
-- Read Functional Section
process(Clock, Read)
begin
if (Clock'event and Clock='1') then
if Enable='1' then
if Read='1' then
-- buildin function conv_integer change the type
-- from std_logic_vector to integer
Data_out <= tmp_ram(conv_integer(Read_Addr));
else
Data_out <= (Data_out'range => 'Z');
end if;
end if;
end if;
end process;
-- Write Functional Section
process(Clock, Write)
begin
if (Clock'event and Clock='1') then
if Enable='1' then
if Write='1' then
tmp_ram(conv_integer(Write_Addr)) <= Data_in;
end if;
end if;
end if;
end process;
end behav;
----------------------------------------------------------------
Error:
Error (10514): VHDL aggregate error at Mem.vhd(41): can't determine type of aggregate -- found 0 possible types
Your faulty code is:
if Read='1' then
-- buildin function conv_integer change the type
-- from std_logic_vector to integer
Data_out <= tmp_ram(conv_integer(Read_Addr));
else
Data_out <= (Data_out'range => 'Z'); -- Faulty line
end if;
Data_out is an integer, not a std_logic_vector or derived type. Thus, it doesn't have a range (only arrays do, std_logic_vector beeing defined as an array of std_logic). Furthermore, it can't take the value of 'Z' since it is not an std_logic; integers can only be assigned integer values.
If you need Data_out to become high-impedance when enable is '1' and read is '0' as you described, you will need your memory output to use std_logic_vector or signed/unsigned.
Also, I should advise you against using integers without range if your target is synthesis. By VHDL standard, integers are 32 bits. Synthesis tool may optimized the netlist and use less bits, but you shouldn't count on it. Either constrain the range of your integers (signal x: integer range -4 to 3) or use signed/unsigned.
I am using modelsim for simulating a pseudo-random pattern generator using the below code. The problem is when i force the data_reg signal to a seed value (ex: 0001010101101111) the data_out shows the same value instead of a random value. i will really appreciate any help i cud get on this one.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff is
Port ( CLK : in std_logic;
RSTn : in std_logic;
D : in std_logic;
Q : out std_logic);
end dff;
architecture Behavioral of dff is
begin
process(CLK)
begin
if CLK'event and CLK='1' then
if RSTn='1' then
Q <= '1';
else
Q <= D;
end if;
end if;
end process;
end Behavioral;
VHDL CODE FOR PRBS Generator using LFSR:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity lfsr is
Port ( CLK : in STD_LOGIC;
RSTn : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (15 downto 0));
end lfsr;
architecture Behavioral of lfsr is
component dff
Port ( CLK : in std_logic;
RSTn : in std_logic;
D : in std_logic;
Q : out std_logic);
end component;
signal data_reg : std_logic_vector(15 downto 0);
signal tap_data : std_logic;
begin
process(CLK)
begin
tap_data <= (data_reg(1) xor data_reg(2)) xor (data_reg(4) xor
data_reg(15));
end process;
stage0: dff
port map(CLK, RSTn, tap_data, data_reg(0));
g0:for i in 0 to 14 generate
stageN: dff
port map(CLK, RSTn, data_reg(i), data_reg(i+1));
end generate;
data_out <= data_reg after 3 ns;
end Behavioral;
First off. In your LFSR you have a process sensitive to CLK which should only be combinational:
process(CLK) -- Not correct
-- Change to the following (or "all" in VHDL-2008)
process(data_reg)
You could also just implement it as a continuous assignment outside of a formal process which is functionally the same in this case.
When you force data_reg to a value you are overriding the normal signal drivers instantiated in the design. In the GUI the force command defaults to "Freeze". Once that is in place, the drivers can't update data_reg because the freeze force is dominant until you cancel it. In the force dialog select the "Deposit" kind to change the state without overriding the drivers on subsequent clocks.
The Modelsim documentation has this to say about the different force kinds:
freeze -- Freezes the item at the specified value until it is forced again or until it is unforced with a noforce command.
drive -- Attaches a driver to the item and drives the specified value until the item is forced again or until it is unforced with a noforce command. This option is illegal for unresolved signals.
deposit -- Sets the item to the specified value. The value remains until there is a subsequent driver transaction, or until the item is forced again, or until it is unforced with a noforce command
Note: While a lot of instructional materials (unfortunately) demonstrate the use of the std_logic_arith and std_logic_unsigned libraries, these are not actual IEEE standards and shouldn't be used in standard conformant VHDL. Use numeric_std instead or, in your case, just eliminate them since you aren't using any arithmetic from those libraries.
I'm trying to assign the value of input aa to the signal t in the code below. It compiles successfully, but there is a warning:
WARNING[9]: C:/Modeltech_5.7f/examples/hassan1.vhd(14): (vcom-1013) Initial value of "t" depends on value of signal "aa".
Here is the code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
use ieee.numeric_std.all;
entity counter is
port(clk :in std_logic;
reset : in std_logic;
aa: in std_logic_vector(3 downto 0);
check : out std_logic_vector(3 downto 0));
end counter;
architecture imp of counter is
signal i:std_logic_vector(3 downto 0):="0000";
signal t:std_logic_vector(3 downto 0):=aa;
begin
process(clk)
begin
if rising_edge(clk) and (t>0) then
t<=t-1;
i<=i+1;
end if;
end process;
check<=i;
end imp;
What should I be doing in order to decrement the input 'aa' in the process? The program is meant to decrement the value at input aa to 0.
It looks like you are trying to implement a down-counter with a load input. In such a counter, when load_enable = '1' you should register the load input value (aa in your case) into an internal signal. When load_enable = '0', you would decrement this count value. Here is a code example that does that:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std_unsigned.all;
entity down_counter is
port (
clock: in std_logic;
reset: in std_logic;
load_enable: in std_logic;
load_data: in std_logic_vector(3 downto 0);
output: out std_logic_vector(3 downto 0)
);
end;
architecture rtl of down_counter is
signal count: std_logic_vector(3 downto 0);
begin
process (clock, reset) begin
if reset then
count <= (others => '0');
elsif rising_edge(clock) then
if load_enable then
count <= load_data;
else
count <= count - 1;
end if;
end if;
end process;
output <= count;
end;
For the record, the code above can be improved, but I didn't want to throw too much stuff at once. It is probably a good idea to use an integer instead of std_logic_vector for your count signal. Also you should check if the count proceeds as you expected, since the example uses the numeric_std_unsigned package. I'd recommend that you change it to numeric_std once you understand the code completely.