Compiling a project in VHDL on Modelsim I encountered the following errors:** Error: C:/Users/User.User-PC/Desktop/progettoasi.vhd(15): near "architecture": syntax error ** Error: C:/Users/User.User-PC/Desktop/progettoasi.vhd(24): near "reg_process": (vcom-1576) expecting END.
This is my code:
enter code here
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity asic is
port ( ck,reset:in std_logic;
req_in: in std_logic_vector(1 downto 0);
req_out: out std_logic_vector(1 downto 0);
req_in_word, response_in_data, nanoinstruction: in std_logic_vector(49 downto 0);
req_out_word, response_out_data: out std_logic_vector(49 downto 0);
response_in, response_out_ack, req_out_ack: in std_logic;
response_out, response_in_ack, req_in_ack: out std_logic);
end asic;
architecture asic_rtl of asic is
signal state,next_state: integer;
signal tmp_source1,tmp_source2 : std_logic_vector(15 downto 0);
signal value1, value2 : std_logic_vector(31 downto 0);
type regsarray IS array (0 to 2**12-1) OF std_logic_vector(49 downto 0);
signal reg_file : regsarray;
signal tmp_nanoinstruction: std_logic_vector(49 downto 0);
signal rw: std_logic;
begin
reg_process:process(ck,reset)
begin
if reset='1' then
state<=1;
elsif rising_edge(ck) then
state<= next_state;
end if;
end process reg_process;
emphasized text
I don't understand what I'm doing wrong.
Thank you in advance.
I agree with Matthew Taylor: the architecture needs to be closed.
Try to add the following to the end of your file:
end asic_rtl;
I made a state automate for this diagram:
Diagram with states
(not a from diagram represents a='0' and b with horizontal bar above represents b='0')
And I write structural and comportamental automate, structural with mux4:1 and 3 d flip-flops.
I made a testbench file in which i give simulate values for a and b variables like this:
a<='0' after 2ns,'1' after 5ns,'0' after 8ns,'1' after 11ns,'1' after 16ns;--se va incepe dupa rn, dupa 2 ns
b<='1' after 11ns,'0' after 13ns;
, for clock:
process
begin
ck<='0';
wait for 0.5ns;
ck<='1';
wait for 0.5ns;
end process;
and for an asynchronous reset:
rn<='1' after 0ns,'0' after 0.2ns,'1' after 2ns;
with this rn i will be starting showing the states and giving a logic value for a and b only after 2 ns
Test result is wrong
The test shows the wrong states for structural description only for first scrolling, after that is equal to the comportamental description. How I can make to show all the curls for this diagram, not only this which is the complete?
I add there the vhdl code for structural and comportamental description, mux4, d flip-flop and test:
Structural:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity automat is
Port ( ck : in STD_LOGIC;
rn : in STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (2 downto 0));
end automat;
architecture structural of automat is
component mux4 is
Port ( a0 : in STD_LOGIC;
a1 : in STD_LOGIC;
i0 : in STD_LOGIC;
i1 : in STD_LOGIC;
i2 : in STD_LOGIC;
i3: in STD_LOGIC;
Y : out STD_LOGIC);
end component;
component dff is
Port ( d : in STD_LOGIC;
ck : in STD_LOGIC;
rn: in STD_LOGIC;
q : out STD_LOGIC;
qn : out STD_LOGIC);
end component;
signal q2,q1,q0,d2,d1,d0:std_logic;
signal an,bn,q0n:std_logic;
signal net1,net2:std_logic;
begin
q0n<=not q0;
q<=q2& q1& q0;
an<=not a;
bn<=not b;
--cele 5 muxuri necesare descrierii structurale
mux412:mux4 port map(i0=>'1',i1=>'0',i2=>'0',i3=>'0',a1=>q0,a0=>b,y=>net1);
mux41:mux4 port map(i0=>'0',i1=>a,i2=>'1',i3=>net1,a1=>q2,a0=>q1,y=>d2);
mux42:mux4 port map(i0=>'1',i1=>an,i2=>q0,i3=>q0n,a1=>q2,a0=>q1,y=>d1);
mux432: mux4 port map(i0=>'0',i1=>'1',i2=>'0',i3=>'0',a1=>q0,a0=>a,y=>net2);
mux43:mux4 port map(i0=>'1',i1=>an,i2=>net2,i3=>q0n,a1=>q2,a0=>q1,y=>d0);
--cele 3 bistabile d necesare
dff2:dff port map(d=>d2, ck=>ck, rn=>rn, q=>q2);
dff1:dff port map(d=>d1, ck=>ck, rn=>rn, q=>q1);
dff0:dff port map(d=>d0, ck=>ck, rn=>rn, q=>q0);
end architecture;
Mux4:1 :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--descriere multiplexor 4:1
entity mux4 is
Port ( a0 : in STD_LOGIC;
a1 : in STD_LOGIC;
i0 : in STD_LOGIC;
i1 : in STD_LOGIC;
i2 : in STD_LOGIC;
i3: in STD_LOGIC;
Y : out STD_LOGIC);
end mux4;
architecture Behavioral of mux4 is
signal A : STD_LOGIC_VECTOR(1 downto 0);
begin
--mux4: process (a1,a0,i0,i1,i2,i3)
--begin
A<=a1 & a0;
Y<=i0 when A="00"
else i1 when A="01"
else i2 when A="10"
else i3;
end Behavioral;
D Flip-Flop:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--descriere bistabil d
entity dff is
Port ( d : in STD_LOGIC;
ck : in STD_LOGIC;
rn: in STD_LOGIC;
q : out STD_LOGIC;
qn : out STD_LOGIC);
end dff;
architecture Behavioral of dff is
begin
flip_flop: process(ck,rn)
begin
if rn='0' then
q <= '0';
else
if rising_edge(ck) then
q <= d;
qn <= not d;
end if;
end if;
end process;
end Behavioral;
Comportamental:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity combinat is
Port ( ck : in STD_LOGIC;
rn : in STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (2 downto 0));
end combinat;
architecture Behavioral of combinat is
signal cur_poz,next_poz:std_logic_vector(2 downto 0);
begin
q<=cur_poz;
process(ck,rn)
begin
if rn='0' then
cur_poz<="000";
elsif rising_edge(ck) then
cur_poz<=next_poz;
end if;
end process;
process(cur_poz,a,b)
begin
case cur_poz is
when "000"=>next_poz<="011";
when "011"=>if a='1' then
next_poz<="100";
else
next_poz<="011";
end if;
when "100"=>if a='1' then
next_poz<="101";
else
next_poz<="100";
end if;
when "101"=>next_poz<="110";
when "110"=>if b='1' then
next_poz<="011";
else
next_poz<="111";
end if;
when "111"=>next_poz<="000";
when others=>next_poz<="000";
end case;
end process;
end Behavioral;
Testbench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test is
-- Port ( );
end test;
architecture Behavioral of test is
component automat is
Port ( ck : in STD_LOGIC;
rn : in STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (2 downto 0));
end component;
component combinat is
Port ( ck : in STD_LOGIC;
rn : in STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (2 downto 0));
end component;
signal ck,rn,a,b:std_logic;
signal qsec,qcomb:std_logic_vector(2 downto 0);
begin
Testare1: automat port map(ck=>ck,--pentru test descriere structurala
rn=>rn,
a=>a,
b=>b,
q=>qsec);
Testare2:combinat port map(ck=>ck,--pentru test descriere comportamentala
rn=>rn,
a=>a,
b=>b,
q=>qcomb);
rn<='1' after 0ns,'0' after 0.2ns,'1' after 2ns;
process
begin
ck<='0';
wait for 0.5ns;
ck<='1';
wait for 0.5ns;
end process;
a<='0' after 2ns,'1' after 5ns,'0' after 8ns,'1' after 11ns,'1' after 16ns;--se va incepe dupa rn, dupa 2 ns
--evaluarea timpilori si valorilor parametrilor conform buclelor din diagrama gasite
b<='1' after 11ns,'0' after 13ns;
--a<='0' after 2ns,'1' after 4ns,'0' after 6ns,'1' after 8ns,'0' after 16ns;
--b<='1' after 8ns,'0' after 10ns;
verificare:process(qsec)--verificare daca corespund rezultatele celor 2 structuri
begin
if qsec/=qcomb then
report "Rezultat al descrierii structurale diferit fata de cea comportamentale";
end if;
end process;
end Behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_bit.all;
use ieee.numeric_std.all;
entity multiplexer is
port (
A,B: in std_logic_vector (7 downto 0);
CI: in std_logic;
CO: out std_logic;
ANS: out std_logic_vector (7 downto 0);
OP: in std_logic_vector(1 downto 0);
EN: in std_logic);
end multiplexer;
architecture archi of multiplexer is
signal tmp: std_logic_vector (8 downto 0);
begin
process (EN) begin
if (EN = '1') Then
case OP is
when "00" =>
tmp <= conv_std_logic_vector((conv_integer(A)+conv_integer(B)+conv_integer(CI)),9);
ANS<= tmp(7 downto 0);
CO <= tmp(8);
when "01" =>
tmp <= conv_std_logic_vector((conv_integer(A)-conv_integer(B)+conv_integer(CI)),9);
ANS<= tmp(7 downto 0);
CO <= tmp(8);
when others => NULL;
end case;
else
NULL;
end if;
end process;
end archi;
error is coming at line 19 No feasible entries for infix operator '=' also Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN. Where am I going wrong?
wave output
Surely this:
EN: in std_logic_vector
should be this:
EN: in std_logic
Your error message is complaining that there is no "=" operator defined that can compare a std_logic_vector to a '1', which is a literal of type std_logic.
I am getting some erros that I cant make sense and was hoping I could get some help.
ERROR: [VRFC 10-469] cannot update 'in' object shift_reg [C:/Users/Darren/Desktop/project_6_1_3/project_6_1_3.srcs/sources_1/new/1Bit_delay_register.vhd:25]
ERROR: [VRFC 10-925] indexed name is not a std_logic_vector [C:/Users/Darren/Desktop/project_6_1_3/project_6_1_3.srcs/sources_1/new/1Bit_delay_register.vhd:27]
ERROR: [VRFC 10-1504] unit simple_one_bit_serial_shift_register_behavior ignored due to previous errors [C:/Users/Darren/Desktop/project_6_1_3/project_6_1_3.srcs/sources_1/new/1Bit_delay_register.vhd:16]
INFO: [VRFC 10-240] VHDL file C:/Users/Darren/Desktop/project_6_1_3/project_6_1_3.srcs/sources_1/new/1Bit_delay_register.vhd ignored due to errors
I have tried altering the code to suit but nothing works ! this is the code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity simple_one_bit_serial_shift_register is
port(
clk : in std_logic;
reset : in std_logic;
shift_in : in std_logic_vector(31 downto 0);
shift_reg : in std_logic_vector(1 downto 0);
shift_out : out std_logic_vector(31 downto 0)
);
end simple_one_bit_serial_shift_register;
architecture simple_one_bit_serial_shift_register_behavior of simple_one_bit_serial_shift_register is
begin
--signal shift_reg : std_logic_vector(31 downto 0);
--signal shift_in : std_logic;
--signal shift_out : std_logic;
process (clk)
begin
if rising_edge(clk) then
shift_reg <= shift_reg(30 downto 0) & shift_in;
end if;
shift_out <= shift_reg(31);
end process;
end simple_one_bit_serial_shift_register_behavior
;
In line 25 the input shift_reg port is assigned, using shift_reg <= ..., but it is not legal to assign to an input port.
In line 27 there is reference to bit 31 in shift_reg(31), but shift_reg only has index 1 and 0 in declaration with shift_reg : in std_logic_vector(1 downto 0);. And indexing a single bit like (31) has type std_logic, which does not match the std_logic_vector type of target shift_out.
I am trying to add two std_logic_vectors using the notation given below:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.NUMERIC_STD.ALL;
entity adder is
port( a:in std_logic_vector(31 downto 0);
b:in std_logic_vector(31 downto 0);
o:out std_logic_vector(31 downto 0));
end adder;
architecture Behavioral of adder is
begin
o<=a+b;
end Behavioral;
One possibility is to generate the result with carry, and then split that afterwards, like:
architecture Behavioral of adder is
signal c_o : std_logic_vector(o'length downto 0); -- Result with carry
signal c : std_logic; -- Carry only
begin
c_o <= ('0' & a) + b; -- Result with carry; extended with '0' to keep carry
o <= c_o(o'range); -- Result without carry
c <= c_o(c_o'left); -- Carry only
end Behavioral;
You can do this. The carry is not saved, but it's being reported that there was an overflow.
function "+" (Add1: std_logic_vector; Add2: std_logic_vector) return std_logic_vector is
variable big_sum: bit_vector(Add1'LENGTH downto 0);
begin
big_sum = Add1 + Add2;
assert big_sum(Add1'LENGTH) = 0
report "overflow"
severity warning;
return big_sum(Add1'LENGTH-1 downto 0);
Of course you'll need to define a new package and also include that package in your already existing file.
o<=std_logic_vector(unsigned(a)+unsigned(b))
Although I suggest you use unsigned/signed on your ports (and have a clock cycle of latency).
If you want the carry
o_with_carry <= std_logic_vector('0'&unsigned(a)+unsigned(b));
o_carry <= o_with_carry(o_with_carry'high);
o <= o_with_carry(o'range);