I'm trying to do a circuit consisting of a 2 to 1 multiplexer (8-bit buses), an 8-bit register and an 8-bit adder. These components are all tested and work as expected.
The thing is: if I try to send the output of the Adder to one of the inputs of the
multiplexer (as seen in the image by the discontinued line), the simulation will stop rather suddenly. If I don't do that and just let ain do its thing, everything will run just as it should, but I do need the output of the adder to be the one inputted to the multiplexer.
The simulation is the following:
The code is:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Sumitas is
port (m : in STD_LOGIC;
clk : in STD_LOGIC;
ain : in STD_LOGIC_VECTOR (7 downto 0);
Add : out STD_LOGIC_VECTOR (7 downto 0));
end Sumitas;
architecture rtl of Sumitas is
component Adder8bit
port (a, b : in STD_LOGIC_VECTOR (7 downto 0);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (7 downto 0);
Cout : out STD_LOGIC);
end component;
component GenericReg
generic (DataWidth : integer := 8);
port (en : in STD_LOGIC;
dataIn : in STD_LOGIC_VECTOR (DataWidth - 1 downto 0);
dataOut : out STD_LOGIC_VECTOR (DataWidth - 1 downto 0));
end component;
component GenericMux2_1
generic (DataWidth : integer := 8);
port (a, b : in STD_LOGIC_VECTOR (DataWidth - 1 downto 0);
Z : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (DataWidth - 1 downto 0));
end component;
constant DW : integer := 8;
signal AddOut_s, MuxOut_s : STD_LOGIC_VECTOR (7 downto 0);
signal PCOut_s : STD_LOGIC_VECTOR (7 downto 0);
begin
m0 : GenericMux2_1
generic map (DataWidth => DW)
port map (a => "00000000",
b => AddOut_s,
Z => m,
S => MuxOut_s);
PC : GenericReg
generic map (DataWidth => DW)
port map (en => clk,
dataIn => MuxOut_s,
dataOut => PCOut_s);
Add0 : Adder8bit
port map (a => "00000001",
b => PCOut_s,
Cin => '0',
S => AddOut_s,
Cout => open);
Add <= AddOut_s;
end rtl;
and the testbench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity bm_Sumitas is
end bm_Sumitas;
architecture benchmark of bm_Sumitas is
component Sumitas
port (m : in STD_LOGIC;
clk : in STD_LOGIC;
ain : in STD_LOGIC_VECTOR (7 downto 0);
Add : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal clk_s, m_s : STD_LOGIC;
signal Add_s, ain_s : STD_LOGIC_VECTOR (7 downto 0);
constant T : time := 2 ns;
begin
benchmark : Sumitas
port map (m => m_s,
clk => clk_s,
ain => ain_s,
Add => Add_s);
clk_proc: process
begin
clk_s <= '0';
wait for T/2;
clk_s <= '1';
wait for T/2;
end process;
bm_proc : process
begin
m_s <= '0';
wait for 10 ns;
m_s <= '1';
wait for 100 ns;
end process;
ains_proc : process
begin
ain_s <= "00001111";
for I in 0 to 250 loop
ain_s <= STD_LOGIC_VECTOR(TO_UNSIGNED(I, ain_s'length));
wait for T;
end loop;
end process;
end benchmark;
How can I do the thing I want? I'm ultimately trying to simulate a computer I designed. I have every component already designed and I'm coupling them together.
Constructing a Minimal, Complete, and Verifiable example requires filling in the missing components:
library ieee;
use ieee.std_logic_1164.all;
entity Adder8bit is
port (a, b : in STD_LOGIC_VECTOR (7 downto 0);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (7 downto 0);
Cout : out STD_LOGIC);
end entity;
architecture foo of adder8bit is
signal sum: std_logic_vector (9 downto 0);
use ieee.numeric_std.all;
begin
sum <= std_logic_vector ( unsigned ('0' & a & cin) +
unsigned ('0' & b & cin ));
s <= sum(8 downto 1);
cout <= sum(9);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
entity GenericReg is
generic (DataWidth : integer := 8);
port (en : in STD_LOGIC;
dataIn : in STD_LOGIC_VECTOR (DataWidth - 1 downto 0);
dataOut : out STD_LOGIC_VECTOR (DataWidth - 1 downto 0));
end entity;
architecture fum of genericreg is
begin
dataout <= datain when en = '1';
end architecture;
with behavioral model substitutes.
(It's not that much work, copy the component declarations paste them, substitute entity for component and add the reserved word is, followed by simple behaviors in architectures.)
It reproduces the symptom you displayed in your simulation waveform:
You can see the essential point of failure occurs when the register enable (ms_s) goes high.
The simulator will report operation on it's STD_OUTPUT:
%: make wave
/usr/local/bin/ghdl -a bm_sumitas.vhdl
/usr/local/bin/ghdl -e bm_sumitas
/usr/local/bin/ghdl -r bm_sumitas --wave=bm_sumitas.ghw --stop-time=40ns
./bm_sumitas:info: simulation stopped #11ns by --stop-delta=5000
/usr/bin/open bm_sumitas.gtkw
%:
Note the simulation stopped at 11 ns because of a process executing repeatedly in delta cycles (simulation time doesn't advance).
This is caused by a gated relaxation oscillator formed by the enabled latch, delay (a delta cycle) and having at least one element of latch input inverting each delta cycle.
The particular simulator used has a delta cycle limitation, which will quit simulation when 5,000 delta cycles occur without simulation time advancing.
The genericreg kept generating events with no time delay in assignment, without an after clause in the waveform, after 0 fs (resolution limit) is assumed.
Essentially when the enable is true the signal will have at least one element change every simulation cycle due to the increment, and assigns the signal a new value for at least one element each simulation cycle without allowing the advancement of simulation time by not going quiescent.
You could note the simulator you used should have produced a 'console' output with a similar message if it were capable (and enabled).
So how it this problem cured? The easiest way is to use a register (not latch) sensitive to a clock edge:
architecture foo of genericreg is
begin
dataout <= datain when rising_edge(en);
end architecture;
Which gives us the full simulation:
hi i' trying to do a 4 bit ripple carry adder with VHDL. The problem is that i'm trying to do a testbench to simulate it in ModelSim, but it doesn't work. This is the code and also the code reported by ModelSim:
Full adder code:
library ieee;
use ieee.std_logic_1164.all;
entity fullAdder is
port( -- Input of the full-adder
a : in std_logic;
-- Input of the full-adder
b : in std_logic;
-- Carry input
c_i : in std_logic;
-- Output of the full-adder
o : out std_logic;
-- Carry output
c_o : out std_logic
);
end fullAdder;
architecture data_flow of fullAdder is
begin
o <= a xor b xor c_i;
c_o <= (a and b) or (b and c_i) or (c_i and a);
end data_flow;
Ripple carry adder code:
library ieee;
use ieee.std_logic_1164.all;
entity Ripple_Carry_Adder is
Port (
A: in std_logic_vector (3 downto 0);
B:in std_logic_vector (3 downto 0);
Cin:in std_logic;
S:out std_logic_vector(3 downto 0);
Cout:out std_logic
);
end Ripple_Carry_Adder;
architecture data_flow2 of Ripple_Carry_Adder is
component fullAdder
Port(
A:in std_logic;
B:in std_logic;
Cin:in std_logic;
S:out std_logic;
Cout:out std_logic
);
end component;
signal c1,c2,c3:STD_LOGIC;
begin
FA1:fullAdder port map(A(0),B(0), Cin, S(0), c1);
FA2:fullAdder port map(A(1),B(1), c1, S(1), c2);
FA3:fullAdder port map(A(2),B(2), c2, S(2), c3);
FA4:fullAdder port map(A(3),B(3), c3, S(3), Cout);
end data_flow2;
code of Ripple carry adder testbench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
ENTITY ripple_carry_adder_tb is
end ripple_carry_adder_tb;
ARCHITECTURE behavior OF ripple_carry_adder_tb is
constant T_CLK : time := 10 ns; -- Clock period
constant T_RESET : time := 25 ns; -- Period before the reset deassertion
COMPONENT Ripple_Carry_Adder
PORT (
A:in std_logic_vector(3 downto 0);
B:in std_logic_vector(3 downto 0);
Cin:in std_logic;
S:out std_logic_vector(3 downto 0);
Cout:out std_logic
);
END COMPONENT;
signal A_tb:std_logic_vector(3 downto 0):="0000";
signal B_tb:std_logic_vector(3 downto 0):="0000";
signal Cin_tb:std_logic:='0';
signal S_tb:std_logic_vector(3 downto 0);
signal Cout_tb:std_logic;
signal clk_tb : std_logic := '0'; -- clock signal, intialized to '0'
signal rst_tb : std_logic := '0'; -- reset signal
signal end_sim : std_logic := '1';
BEGIN
clk_tb <= (not(clk_tb) and end_sim) after T_CLK / 2; -- The clock toggles after T_CLK / 2 when end_sim is high. When end_sim is forced low, the clock stops toggling and the simulation ends.
rst_tb <= '1' after T_RESET;
RP_1: Ripple_Carry_Adder PORT MAP(A=>A_tb,B=>B_tb,Cin=>Cin_tb,S=>S_tb,Cout=>Cout_tb);
d_process: process(clk_tb, rst_tb) -- process used to make the testbench signals change synchronously with the rising edge of the clock
variable t : integer := 0; -- variable used to count the clock cycle after the reset
begin
if(rst_tb = '0') then
A_tb <= "0000";
B_tb <= "0000";
Cin_tb<='0';
t := 0;
elsif(rising_edge(clk_tb)) then
A_tb<=A_tb+1;
B_tb<=B_tb+1;
t := t + 1;
if (t>32) then
end_sim <= '0';
end if;
end if;
end process;
END;
and this is errors reported by ModelSim when i trying to start simulation:
# ** Fatal: (vsim-3817) Port "c_i" of entity "fulladder" is not in the component being instantiated.
# Time: 0 ns Iteration: 0 Instance: /ripple_carry_adder_tb/RP_1/FA1 File:
C:/Users/utente/Desktop/full_adder.vhd Line: 11
# FATAL ERROR while loading design
# Error loading design
Why doesn't work? Thanks
I am trying to run post synthesis functional simulation. When i run the code for behavioral simulation, i get the output and everything runs fine. Bu when i run the post synthesis i get the following error:
ERROR: [VRFC 10-3146] binding entity 'rippleadder_nbit' does not have generic 'n' [C:/Users/gauta/Assignment4/Assignment4.srcs/sim_1/new/tb_ripplenbit.vhd:41]
Can someone explain me what i need to do please. I am a novice in Vivado and very confused on how to use this
My Rippleadder Code is:
entity rippleadder_nbit is
generic(n: natural);
Port ( cin_ra : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (n-1 downto 0);
b : in STD_LOGIC_VECTOR (n-1 downto 0);
s_ra : out STD_LOGIC_VECTOR (n-1 downto 0);
cout_ra : out STD_LOGIC);
end rippleadder_nbit;
architecture Behavioral of rippleadder_nbit is
component fulladder port(
x_fa : in STD_LOGIC;
y_fa : in STD_LOGIC;
z_fa : in STD_LOGIC;
s_fa : out STD_LOGIC;
c_fa : out STD_LOGIC);
end component;
signal r: std_logic_vector(n downto 0);
begin
r(0) <= cin_ra;
cout_ra <= r(n);
FA: for i in 0 to n-1 generate
FA_i : fulladder port map(r(i),a(i),b(i),s_ra(i),r(i+1));
end generate;
end Behavioral;
my testbench is as follows:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_ripplenbit is
-- Port ( s: std_logic_vector(2 downto 0);
-- cout: std_logic);
end tb_ripplenbit;
architecture Behavioral of tb_ripplenbit is
component rippleadder_nbit
generic(n: natural);
Port ( cin_ra : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (n-1 downto 0);
b : in STD_LOGIC_VECTOR (n-1 downto 0);
s_ra : out STD_LOGIC_VECTOR (n-1 downto 0);
cout_ra : out STD_LOGIC);
end component;
signal a,b,sin : STD_LOGIC_VECTOR (3 downto 0);
signal cin,carry_out : std_logic;
constant c : integer :=4;
begin
a <= "0000", "0001" after 50 ns, "0101" after 100ns;
b <= "0010", "0011" after 50 ns, "1010" after 100 ns;
cin <= '1', '0' after 50 ns;
UUT1 : rippleadder_nbit generic map(n => c) port map(cin_ra => cin,a=>a,b=>b,s_ra=>sin,cout_ra =>carry_out);
end Behavioral;
In post-synthesis/post-implementation, the generics(constant) are deleted and usage of those generics are replaced with the constant value
In test bench, you had instance w.r.t to behavioural model(with generic involved) so the same test bench won't be applicable for post-synth/post-implementation simulation
Source: Xilinx Forums
I have this very simple 16-bit and gate written in structural form in VHDL:
The files are uploaded here.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and_16bit is
Port (
A : in std_logic_vector(15 downto 0);
B : in std_logic_vector(15 downto 0);
Clk : in STD_LOGIC;
--Rst : in STD_LOGIC;
C : out std_logic_vector(15 downto 0) );
end and_16bit;
architecture Behavioral of and_16bit is
component and_1bit is
Port (
A : in std_logic;
B : in std_logic;
C : out std_logic );
end component;
signal s : std_logic_vector(15 downto 0);
begin
ands: for i in 15 downto 0 generate
and_1bit_x: and_1bit port map (A => A(i), B => B(i), C => s(i));
end generate;
process(Clk)
begin
if rising_edge(Clk) then
C <= s;
end if;
end process;
end Behavioral;
In order to update the output in the rising edge of the clock, I have defined this "s" signal. I wonder if this is the correct way to update the output in structural VHDL codes? what should I do to scape the unknown output for the first output?
Any comments will be a great help.
It's better to put the sequential process into a submodule and instantiate it in the top-level (and_16bit). Then your top-level will be more structural.
You can have one instance for each bit as you did for and_1bit.
For example, this module is a 1-bit register.
entity dff_1bit is
Port (
D : in std_logic;
Clk : in std_logic;
Q : out std_logic );
end dff_1bit;
architecture Behavioral of dff_1bit is
begin
process(Clk)
begin
if rising_edge(Clk) then
Q <= D;
end if;
end process;
end Behavioral;
Then you can instantiate it in and_16bit, inside the same generate block.
dff_1bit_x: dff_1bit port map (D => s(i), Clk => Clk, Q => C(i));
I am implementing a multiplier in which i multiply A (8 bits) and B (8 bits), and store result at S. Number of bit required for output S is 16 bits. S have higher part SH and lower part SL.Every time i shift ,add operation is performed
i am getting following errors in my controller part :-
Attribute event requires a static signal prefix
is not declared.
"**" expects 2 arguments
and my code is:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity PIPO is
port (reset: in std_logic ;
B:IN STD_LOGIC_VECTOR (7 downto 0 );
LOAD:in std_logic ;
SHIFT:in std_logic ;
ADD:in std_logic ;
Sum:IN STD_LOGIC_VECTOR (7 downto 0 );
C_out:in std_logic ;
CLK:in std_logic ;
result: out STD_LOGIC_VECTOR (15 downto 0) ;
LSB:out std_logic ;
TB:out std_logic_vector (7 downto 0) );
end ;
architecture rtl OF PIPO is
signal temp1 : std_logic_vector(15 downto 0);
----temp2 -add
signal temp2 : std_logic ;
begin
process (CLK, reset)
begin
if reset='0' then
temp1<= (others =>'0');
temp2<= '0';
elsif (CLK'event and CLK='1') then
if LOAD ='1' then
temp1(7 downto 0) <= B;
temp1(15 downto 8) <= (others => '0');
end if ;
if ADD= '1' then
temp2 <='1';
end if;
if SHIFT= '1' then
if ADD= '1' then
------adder result ko add n shift
temp2<= '0';
temp1<=C_out & Sum & temp1( 7 downto 1 );
else
----only shift
temp1<= '0' & temp1( 15 downto 1 );
end if;
end if;
end if;
end process;
LSB <=temp1(0);
result<=temp1( 15 downto 0 );
TB <=temp1(15 downto 8);
end architecture rtl;
-------------------------------------------
-------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Controller is
Port ( ADD :OUT STD_LOGIC;
SHIFT:OUT STD_LOGIC;
LOAD:OUT STD_LOGIC;
STOP:OUT STD_LOGIC;
STRT:IN STD_LOGIC;
LSB:IN STD_LOGIC;
CLK:IN STD_LOGIC;
reset:IN STD_LOGIC );
end ;
architecture rtl OF Contoller is
---RTL level code is inherently synchronous
signal count : unsigned (2 downto 0);
----differnt states
type state_typ is ( IDLE, INIT, TEST, ADDs, SHIFTs );
signal state : state_typ;
begin
--controller : process (ADD,SHIFT,LOAD,STOP,STRT,LSB,CLK,reset)
process (state)--(CLK, reset,ADD,SHIFT,LOAD,STOP,STRT,LSB)
begin
if reset='0' then
state <= IDLE;
count <= "000";
elsif (CLK'event and CLK='1') then
case state is
when IDLE =>
if STRT = '1' then
--- if STRT = '1' then
state <= INIT;
else
state <= IDLE;
end if;
when INIT =>
state <= TEST;
when TEST =>
if LSB = '0' then
state <= SHIFTs;
else
state <= ADDs;
end if;
when ADDs =>
state <= SHIFTs;
when SHIFTs =>
if count = "111" then
count <= "000";
state <= IDLE;
else
count<= std_logic_vector(unsigned(count) + 1);
state <= TEST;
end if;
end case;
end if;
end process ;
STOP <= '1' when state = IDLE else '0';
ADD <= '1' when state = ADDs else '0';
SHIFT <= '1' when state = SHIFTs else '0';
LOAD <= '1' when state = INIT else '0';
end architecture rtl;
----------------------------------------------
--------------------------------------------
---multiplicand
library ieee;
use ieee.std_logic_1164.all;
entity multiplicand is
port (A : in std_logic(7 downto 0);
reset :in std_logic;
LOAD : in std_logic;
TA : OUT STD_LOGIC(7 downto 0);
CLK : in std_logic );
end entity;
architecture rtl OF multiplicand is
begin
process (CLK, reset)
begin
if reset='0' then
TA <= (others =>'0'); -- initialize
elsif (CLK'event and CLK='1') then
if LOAD_cmd = '1' then
TA(7 downto 0) <= A_in; -- load B_in into register
end if;
end if ;
end process;
end architecture rtl;
------------------------------------------------------
------------------------------------------------------
---Full Adder
library ieee;
use ieee.std_logic_1164.all;
entity Full_Adder is
port (A : in std_logic;
B : in std_logic;
C_in : in std_logic;
Sum : out std_logic ;
C_out : out std_logic);
end;
architecture struc of Full_Adder is
begin
Sum <= A xor B xor C_in;
C_out <= (A and B) or (A and C_in) or (B and C_in);
end struc;
------------------------------------------------------------
-------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Adder is
Port ( TA : in STD_LOGIC_VECTOR (7 downto 0);
TB : in STD_LOGIC_VECTOR (7 downto 0);
Sum : out STD_LOGIC_VECTOR (7 downto 0);
C_in : in STD_LOGIC;
C_out : out STD_LOGIC);
end Adder;
architecture struc of Adder is
component Full_Adder is
port(A : in std_logic;
B : in std_logic;
C_in : in std_logic;
Sum : out std_logic ;
C_out : out std_logic);
end component;
signal C: std_logic_vector (7 downto 0);
begin
FA0:Full_Adder port map(TA(0), TB(0), C_in, Sum(0), C(0));
FA1: Full_Adder port map(TA(1), TB(1), C(0), Sum(1), C(1));
FA3: Full_Adder port map(TA(2),TB(2), C(1), Sum(2), C(2));
FA4: Full_Adder port map(TA(3), TB(3), C(2), Sum(3), C(3));
FA5: Full_Adder port map(TA(4), TB(4), C(3), Sum(4), C(4));
FA6: Full_Adder port map(TA(5), TB(5), C(4), Sum(5), C(5));
FA7: Full_Adder port map(TA(6), TB(6), C(5), Sum(6), C(6));
FA8: Full_Adder port map(TA(7), TB(7), C(6), Sum(7), C(7));
C_out <= C(7);
end struc;
------------------------------------------------------------
------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity multiplier is
Port ( num1 : in STD_LOGIC_VECTOR (7 downto 0);
num2 : in STD_LOGIC_VECTOR (7 downto 0);
result : out STD_LOGIC_VECTOR (15 downto 0);
CLK:in std_logic ;
reset:IN STD_LOGIC;
STRT:IN STD_LOGIC;
STOP:OUT STD_LOGIC );
end multiplier;
architecture rtl of Multiplier is
signal ADD :STD_LOGIC;
signal SHIFT :STD_LOGIC;
signal LOAD :STD_LOGIC;
signal LSB :STD_LOGIC;
signal A : STD_LOGIC_VECTOR (7 downto 0);
signal B :STD_LOGIC_VECTOR (7 downto 0);
signal Sum:STD_LOGIC_VECTOR (7 downto 0);
signal C_out:STD_LOGIC;
component Controller
port (
ADD :OUT STD_LOGIC;
SHIFT:OUT STD_LOGIC;
LOAD:OUT STD_LOGIC;
STOP:OUT STD_LOGIC;
STRT:IN STD_LOGIC;
LSB:IN STD_LOGIC;
CLK:IN STD_LOGIC;
reset:IN STD_LOGIC );
end component;
component Adder
port (
TA : in STD_LOGIC_VECTOR (7 downto 0);
TB : in STD_LOGIC_VECTOR (7 downto 0);
Sum : out STD_LOGIC_VECTOR (7 downto 0);
C_in : in STD_LOGIC;
C_out : out STD_LOGIC);
end component;
component PIPO
port (reset: in std_logic ;
B:IN STD_LOGIC_VECTOR (7 downto 0 );
LOAD:in std_logic ;
SHIFT:in std_logic ;
ADD:in std_logic ;
Sum:IN STD_LOGIC_VECTOR (7 downto 0 );
C_out:in std_logic ;
CLK:in std_logic ;
result: out STD_LOGIC_VECTOR (15 downto 0) ;
LSB:out std_logic ;
TB:out std_logic );
end component;
component multiplicand
port (A : in std_logic (7 downto 0);
reset :in std_logic;
LOAD : in std_logic;
TA : OUT STD_LOGIC(7 downto 0);
CLK : in std_logic );
end component ;
begin
inst_Controller: Controller
port map (ADD => ADD,
SHIFT =>SHIFT,
LOAD =>LOAD ,
STOP =>STOP,
STRT =>STRT,
LSB =>LSB ,
CLK =>CLK ,
reset =>reset
);
inst_multiplicand :multiplicand
port map (A =>A,
reset=>reset,
LOAD =>LOAD,
TA => TA(7 downto 0),
CLK => CLK
);
inst_PIPO :PIPO
port map ( reset => reset,
B => B ,
LOAD =>LOAD,
SHIFT=>SHIFT,
ADD=>ADD,
Sum=>Sum,
C_out=>C_out,
CLK=>CLK,
result=>result,
LSB=>LSB,
TB=>TB
);
inst_Full_Adder : Full_Adder
port map ( TA => TA,
TB =>TB,
Sum=>Sum ,
C_in=>C_in,
C_out=>C_out
);
end rtl;
Actually the space between CLK and the apostrophe/tick isn't significant
david_koontz#Macbook: token_test
elsif (CLK 'event and CLK ='1') then
KEYWD_ELSIF (151) elsif
DELIM_LEFT_PAREN ( 9) (
IDENTIFIER_TOKEN (128) CLK
DELIM_APOSTROPHE ( 8) '
IDENTIFIER_TOKEN (128) event
KEYWD_AND (134) and
IDENTIFIER_TOKEN (128) CLK
DELIM_EQUAL ( 25) =
CHAR_LIT_TOKEN ( 2) '1'
DELIM_RIGHT_PAREN ( 10) )
KEYWD_THEN (211) then
gives the same answer as:
david_koontz#Macbook: token_test
elsif (CLK'event and CLK ='1') then
KEYWD_ELSIF (151) elsif
DELIM_LEFT_PAREN ( 9) (
IDENTIFIER_TOKEN (128) CLK
DELIM_APOSTROPHE ( 8) '
IDENTIFIER_TOKEN (128) event
KEYWD_AND (134) and
IDENTIFIER_TOKEN (128) CLK
DELIM_EQUAL ( 25) =
CHAR_LIT_TOKEN ( 2) '1'
DELIM_RIGHT_PAREN ( 10) )
KEYWD_THEN (211) then
In vhdl, there is no lexical element parsing requiring a lack of white space. (Sorry Russel).
Correcting the other syntax ambiguities of your code (see below, missing context clause, Controller misspelled in the architecture declaration, count used as both a scalar and array subtype), results in two different VHDL analyzers swallowing the space between CLK and ' just fine.
The problem is in the tool you are using not actually being standard compliant or the code you present as having the problem isn't actually representational of the code generating the error. If a non-compliant tool it's likely a shortcoming you can live with, although there may be more things a bit more irksome.
david_koontz#Macbook: ghdl -a controller.vhdl
david_koontz#Macbook: nvc -a controller.vhdl
david_koontz#Macbook:
(no errors, it also elaborates without a test bench in ghdl, nvc disallows top level ports - which it is permitted to do by the standard)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Controller is
Port (
ADD: OUT STD_LOGIC;
SHIFT: OUT STD_LOGIC;
LOAD: OUT STD_LOGIC;
STOP: OUT STD_LOGIC;
STRT: IN STD_LOGIC;
LSB: IN STD_LOGIC;
CLK: IN STD_LOGIC;
reset: IN STD_LOGIC
);
end entity;
architecture rtl OF Controller is
---RTL level code is inherently synchronous
signal count : std_logic_vector (2 downto 0);
----differnt states
type state_typ is ( IDLE, INIT, TEST, ADDs, SHIFTs );
signal state : state_typ;
begin
NOLABEL:
process (CLK, reset)
begin
if reset='0' then
state <= IDLE;
count <= "000";
elsif (CLK 'event and CLK ='1') then
case state is
when IDLE =>
if STRT = '1' then
state <= INIT;
else
state <= IDLE;
end if;
when INIT =>
state <= TEST;
when TEST =>
if LSB = '0' then
state <= SHIFTs;
else
state <= ADDs;
end if;
when ADDs =>
state <= SHIFTs;
when SHIFTs =>
if count = "111" then -- verify if finished
count <= "000"; -- re-initialize counter
state <= IDLE; -- ready for next multiply
else
count <= -- increment counter
std_logic_vector(unsigned(count) + 1);
state <= TEST;
end if;
end case;
end if;
end process;
---end generate; ???
STOP <= '1' when state = IDLE else '0';
ADD <= '1' when state = ADDs else '0';
SHIFT <= '1' when state = SHIFTs else '0';
LOAD <= '1' when state = INIT else '0';
end architecture rtl;
The error message appears to stem from the signal CLK (the prefix for the event attribtute). There is no other use of the event attribute in your code presented with the question. A signal is one of the elements of entity_class that can be decorated with an attribute.
In the VHDL LRM's section on predefined attributes 'EVENT can only decorate a signal, and CLK is a signal (declared in a port). In that section the prefix is required to be denoted by a static signal name.
Is CLK a static signal name? Yes it is. It's a scalar subtype declared in the entity declaration and is locally static (available at analysis time - it's a scalar, a simple name and not involving a generic).
And about now you might get why someone would wonder if the code in the question is representational of the code generating the error or the VHDL tool used is not compliant.
The error message you report is usually associated with trying to use 'EVENT with an indexed signal name, e.g. w(i)'event. (See Signal attributes on a signal vector).
You're going to kick yourself for this one:
elsif (CLK 'event and CLK ='1') then
Should be:
elsif (CLK'event and CLK ='1') then
See the difference?
Even better:
elsif rising_edge(CLK) then
It seems you're missing a clk entry in the process
Change the line reading:
process (state)--(CLK, reset,ADD,SHIFT,LOAD,STOP,STRT,LSB)
to read:
process (clk, reset)