Using a Stratix II FPGA is it possible to generate a clock output with a frequency much higher than 200MHz? (Up to 400 or 500MHz) If so how can I achieve this?
I used a PLL to generate 200MHz out of a 100MHz clock and this seems to work. But turning the PLL to 250MHz will make the TimeQuest Timing Analyzer reporting a negative setup slack for the PLL in the slow model. So I wonder if there is a better way to generate such high frequency clock outputs...
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Is it possible to generate a 1000 MHz clock from a 100 MHz in VHDL ?
I want to create a 1ns counter and my fpga has a 100 MHz clock!
Clock generation is usually done with Phase Locked Loop (PLL) or Digital Clock Manager (DCM), available in the FPGA as dedicated FPGA hardware resources.
If you want to scale up a clock, like going from 100 MHz to 1000 MHz, then you definitely need to use the dedicated FPGA hardware resources in order to get a stable and manageable implementation.
However, a clock of 1000 MHz is very likely too fast for use in any general logic, like a standard counter. Clocks that fast are typically only used for some very special purposes like internally in a SERDES etc.
So you probably have to consider some different way to implement the required functionality.
Is the internal clock on the ATTiny85 sufficiently accurate for one-wire timing?
Per https://learn.sparkfun.com/tutorials/ws2812-breakout-hookup-guide one-wire timing seems to need accuracy around the 0.05us range, so a 10% clock error on the AVR at 8MHZ would cause 0.0125us sized timing differences (assuming the 10% error figure is accurate, and that it's 10% error on frequency, not +/- 10% variance on each pulse).
Not a ton of margin - but is it good enough?
First of all, WS2812 LEDs are not the 1-wire.
The control protocol of WS2812 is described in the datasheet
The short answer is yes, ATTiny85, also the whole AVR family have enough clock accuracy to control the WS2812 chain. But routine should be written at assembler, also no interrupts should be allowed, to guarantee match the timing requests. When doing the programming well, 8MHz speed of the internal oscillator may be enough to output the different data to two WS2812 chains simultaneously.
So, when running 8MHz ±10%, the one clock cycle would be 112...138 ns.
The datasheet requires (with 150ns tolerance):
When transmitting "one": high level to be 550...850ns; - 6 clock cycles (672...828) matches this range (also 5 clock cycles (560...690ns) matches)
following low level - 450...750ns; - 5 cycles (560...690ns)
When transmitting "zero": high level 200...500ns; - 3 cycles (336...414ns)
following low level 650...950ns; - 6 cycles (672...828).
So, as you can see, considering tolerance ±10% of the clock's source, you can find the integer number of cycles which will guarantee match to the required intervals.
Speaking from the experience, it still be working if the low level, which follows the pulse, will be extended for a couple hundreds of nanoseconds.
There are known issues using internal oscilator with UART - should be timed to 2% accuracy while the internal oscilator can be up to 10% off with factory setting. While it can be calibrated(AVR has register OSCCAL for that purpose), its frequency is influenced by temperature.
It is worth the try, but might not to be reliable with temperature changes or fluctuating operating voltage.
References: ATmega's internal oscillator - how bad is it, Timing accuracy on tiny2313, Tuning internal oscilator
The timing requirements of NeoPixels (WS2812B) are wide enough that the only really critical part is the minimum width of a 1 bit. The ATtiny85 at 16Mhz is plenty fast to drive a string of them from a GPIO pin. At 8Mhz, it may not work (I haven't tried yet). I just released a small Arduino sketch which allows you to control NeoPixel strings of any length on a ATtiny85 without using any RAM.
https://github.com/bitbank2/NeoPixel
For devices with hardware SPI (e.g. ATMega328p), it's better to use SPI to shift out the bits (also included in my code).
I have been using FRDM_KL46Z development board to do some IR communication experiment. Right now, I got two PWM outputs with same setting (50% duty cycle, 38 kHz) had different voltage levels. When both were idle, one was 1.56V, but another was 3.30V. When the outputs were used to power the same IR emitter, the voltages were changed to 1.13V and 2.29V.
And why couldn't I use one PWM output to power two IR emitters at the same time? When I tried to do this, it seemed that the frequency was changed, so two IR receivers could not work.
I am not an expert in freescale, but how are you controlling your pwm? I'm guessing each pwm comes from a separate timer, maybe they are set up differently. Like one is in 16 bit mode (the 3.3V) and the other in 32 (1.56v) in that case even if they have the same limit in the counter ((2^17 - 1) / 2) would be 50% duty cycle of a 16 bit timer. But in a 32 bit, that same value would only be 25% duty so, one output would be ~1/2 the voltage of the other. SO I suggest checking the timer setup.
The reason the voltage changed is because the IR emmiters were loading the circuit. In an ideal situation this wouldn't happen, but if a source is giving too much current the voltage usually drops a bit.
I need develope synthesizable custom verilog code for generating a higher frequency clock from low frequency clock i.e from 50 MHz clock i need to generate 100 MHZ clock . kindly help how to do the same.
A pure Verilog solution is not stable, so dedicated FPGA resources must be used.
Please see this previous answer; it applies to Verilog also, even through tagged VHDL.
My spartan 3a fpga board has a 50mhz clock while implementing a microblaze with ram ddr2 , it required a frequency of 62mhz which was edited by my program , when asked about this , they told me that 60mhz clock is used to generate other clocks internally but how does a 50mhz clock produce a 62mhz clock which is higher !?
in Xilinx Spartan devices you can use so called DCMs (digital clock managers) that give you a whole lot of possibilities; see Spartan User Guide or Xilinx Spartan 3 DCM. with the synthesizer option, clock multiplication/division is possible.
There are built in technologies that multiply the clock to higher frequencies. See Frequency Multiplier and Phase Locked Loop
under your design name in Implementation window in ISE right click and add new sorce select IPcore then select clocking wizard you can enter the primary freq : 50 mhz and required out freq: 62 mhz and the core generator will do it for you.