I have a question on synthesis in VHDL that I'm hoping some of you can help me with. I have the following model for a adder :
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Q3a IS
PORT (A_MSB,B_MSB,A_LSB,B_LSB : IN std_logic_vector(3 DOWNTO 0):="0000";
SEL : IN std_logic:='0';
CARRY : OUT std_logic:='0';
OUTPUT : OUT std_logic_vector(7 DOWNTO 0):="00000000");
END ENTITY Q3a;
ARCHITECTURE behavioral OF Q3a IS
SIGNAL A,B,SUM,B_NEG : std_logic_vector(8 DOWNTO 0);
BEGIN
A <= (A_MSB(3) & '0' & A_MSB(2 DOWNTO 0) & A_LSB) WHEN A_MSB(3) = '0' ELSE
(A_MSB(3) & '1' & A_MSB(2 DOWNTO 0) & A_LSB);
B <= (B_MSB(3) & '0' & B_MSB(2 DOWNTO 0) & B_LSB) WHEN B_MSB(3) = '0' ELSE
(B_MSB(3) & '1' & B_MSB(2 DOWNTO 0) & B_LSB);
B_NEG <= std_logic_vector(signed(not(B_MSB(3) & '0' & B_MSB(2 DOWNTO 0) & B_LSB))+1);
SUM <= std_logic_vector(signed(A)+ signed(B)) WHEN SEL = '0' ELSE
std_logic_vector(signed(A)+ signed(B_NEG));
CARRY <= SUM(7);
OUTPUT <= SUM(8) & SUM(6 DOWNTO 0);
END ARCHITECTURE behavioral;
The model works OK'ish a few glitches. When I look at it though I see 3 multiplexers, one for A, one for B, and one for input selection to the adder. When I open the model with RTL viewer on Quartus II. I get this:
Which to me looks like 4 adders and a multiplexer. Can anyone share some light with me on this?
Cheers
D
If I understand you correctly, you want one adder for a+b and a+b_neg, and a mux that selects between b or b_neg.
You didn't write it explicitly, you need to write it like so
architecture behavioral of Q3a is
signal a,b,sum,b_neg : std_logic_vector(8 downto 0);
signal b_addr : std_logic_vector(8 downto 0);
begin
a <= (a_msb(3) & a_msb & a_lsb);
b <= (b_msb(3) & b_msb & b_lsb);
b_neg <= std_logic_vector(-signed(b));
b_addr <= b when sel = '0' else b_neg;
sum <= std_logic_vector(signed(a)+ signed(b_addr));
carry <= sum(7);
output <= sum(8) & sum(6 downto 0);
end architecture behavioral;
Hopes that help you.
There is a single mux in your design, as Brian noted the logic for A is simplified to A <= A_MSB(3) & A_MSG & A_LSB , which doesn't have a mux.
Your logic for B_neg is wrong, as it will only give you -B when B is positive. If you use B_neg <= std_logic_vector(signed(not(B))+1); you will have different synthesis results.
There should be 3 adders, one for B_neg, one for A+B and one for A+B_neg. However, I suspect because of the way you define B_neg with a constant '0', the synthesizer outsmart you and divide the B_neg adder into 2 smaller adder.
You don't have to define B_neg as "not B + 1", i.e. two's complement unary minus definition. It is better, for readability to use B_neg <= std_logic_vector(-signed(B)); or SUM <= std_logic_vector(signed(A)+signed(B)) when SEL = '0' else std_logic_vector(signed(A)-signed(B));
After making the changes I have the following Architecture:
ARCHITECTURE behavioral OF Q3a IS
SIGNAL A,B,SUM,B_NEG : std_logic_vector(8 DOWNTO 0);
BEGIN
A <= (A_MSB(3) & A_MSB & A_LSB);
B <= (B_MSB(3) & B_MSB & B_LSB);
B_NEG <= std_logic_vector(-signed(B));
SUM <= std_logic_vector(signed(A)+ signed(B)) WHEN SEL = '0' ELSE
std_logic_vector(signed(A)+ signed(B_NEG));
CARRY <= SUM(7);
OUTPUT <= SUM(8) & SUM(6 DOWNTO 0);
END ARCHITECTURE behavioral;
The RTL synthesis diagram has changed to:
Just like Jonathan suggested it would. I understand it needs 1 adder for B_NEG, but, but is their a reason for it having separate adders for A+B and A+B_NEG followed by a Mux, instead of having a Mux and two adders? Something more like this:
Is this just synthesis choice?
Related
How can I implement Division and Multiplication manually in VHDL? That is; using Left & Right Shift and without the need for numeric_std (If possible).
A possible soulution:
library ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Shifter is
generic(
num_length : integer := 32
);
port(
EN : in std_logic;
clk : in std_logic;
number : in std_logic_vector((num_length - 1) downto 0);
dir : in std_logic;
result : out std_logic_vector((num_length - 1) downto 0));
end Shifter;
architecture Beh of Shifter is
signal temp : std_logic_vector((num_length - 1) downto 0);
begin
result <= std_logic_vector(temp);
process(EN, clk) is
begin
if EN = '0' then
temp <= (OTHERS => '0');
elsif rising_edge(clk) then
case dir is
when '0' => temp <= '0' & number((num_length - 2) downto 0);
when '1' => temp <= number((num_length - 2) downto 0) & '0';
end case;
end if;
end process;
end Beh;
Every clk cycle the position increases/decreases (depends on dir setting)
It can also be released with loops so that the module can increase/decrease more than one bit at a cycle.
Important: It is only possible to increase/decrease by the power of 2 (2,4,8,16,32,...) with shifting
So I've been working on some homework for my VHDL course and I can't seem to understand this problem.
The point here is to create the adder/subtractor of an ALU that works both on 2's complement and unsigned 32-bit buses, which is why I have a condition called sub_mode ( A - B = A + !B + 1 ) which will also be the carry-in when activated.
The rest of the different inputs and outputs are pretty self-explanatory.
My problem is with the testbenching of such component where, even though carry_temp and r_temp have been initialized in declaration section of the architecture, end up showing up undefined. I have guessed that it is due to the for loop within the process screwing everything up. Would that be an accurate guess? And if yes, is it possible to proceed to add two bit buses together without having to fully create an n-bit adder made from n 1-bit adder components?
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity add_sub is
port(
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
sub_mode : in std_logic;
carry : out std_logic;
zero : out std_logic;
r : out std_logic_vector(31 downto 0)
);
end add_sub;
architecture synth of add_sub is
signal cond_inv : std_logic_vector(31 downto 0);
signal carry_temp : std_logic_vector(32 downto 0) := (others => '0');
signal r_temp : std_logic_vector(31 downto 0) := (others => '0');
begin
behave : process(a,b,sub_mode)
begin
if sub_mode = '1' then
cond_inv <= b xor x"ffffffff";
else
cond_inv <= b;
end if;
carry_temp(0) <= sub_mode;
for i in 0 to 31 loop
r_temp(i) <= a(i) xor cond_inv(i) xor carry_temp(i);
carry_temp(i+1) <=
(a(i) and cond_inv(i)) or
(a(i) and carry_temp(i)) or
(cond_inv(i)and carry_temp(i));
end loop;
if r_temp = x"00000000" then
zero <= '1';
else
zero <= '0';
end if;
r <= r_temp;
carry <= carry_temp(32);
end process behave;
end synth;
I am making an UART transceiver, and In that for Receiver section, I need a SIPO to convert the serial data into parallel one, A web search threw out a code which does the required function, I am not able to understand how this particular code works, googling didn't help. I am grateful if someone can point out how this works
library ieee;
use ieee.std_logic_1164.all;
entity RXN_CNTRL is
port(
reset : in std_logic;
clk : in std_logic;
din : in std_logic;
dout : out std_logic_vector(3 downto 0)
);
end entity;
architecture behave of RXN_CNTRL is
signal s : std_logic_vector(3 downto 0) := "0000" ;
begin
sipo : process (clk, reset)
begin
if (reset='1') then
s <= "0000";
elsif (rising_edge (clk)) then
s <= (din & s(3 downto 1));
end if;
end process;
dout <= s;
end architecture;
I am not able to understand how the line s <= (din & s(3 downto 1));
works. please clear me in this, I am new to vhdl and want to learn how this works. Thanks
In VHDL & is the concatenation operator. It is used to make bigger arrays from smaller arrays and single array elements by concatenating them, ie joining them together. So,
s <= (din & s(3 downto 1));
takes the single bit din and joins it to the leftmost 3 bits of s (s(3 downto 1)) to give a new value of s:
din s(3) s(2) s(1)
So, you can see that s has been shifted one place to the right and the empty space has been filled with din - exactly the behaviour you'd want for a SIPO.
In VHDL I would recommend always using the combination of concatenation and slicing (taking part of an array, like s(3 downto 1)) for implementing shift-registers and so on. The builtin operators (sla etc) behave in strange ways.
& is the concatenation operator in VHDL.
So what this does is to shift in the newly received bit (din) into s from the left (disposing the lowest bit of s).
Suppose s is "0000" initially. If din = '1', then s <= din & s(3 downto 1) takes din ('1'), concatenates s(3 downto 1)("000") to it and assigns the result to s. The lowest bit of s is 'lost' through this.
I recommend playing through this until you understand what happens.
I am trying to make set&load d-flip flop code(synch) but it keeps giving me count <= '0' & d; it has 2 elements but must have 9 elements error.Thanks in advance
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity syn is
port (
clk : in std_logic;
rst_n : in std_logic;
d : in std_logic;
ld : in std_logic;
q : out std_logic_vector(7 downto 0);
co : out std_logic);
end syn;
architecture rtl of syn is
signal count : std_logic_vector(8 downto 0);
begin
co <= count(8);
q <= count(7 downto 0);
process (clk)
begin
if (clk'event and clk = '1') then
if (rst_n = '0') then
count <= (others => '0'); -- sync reset
elsif (ld = '1') then
count <= '0' & d; -- sync load
else
count <= count + 1; -- sync increment
end if;
end if;
end process;
end rtl;
Input d is std_logic, so '0' & d is 2 bit vector. Count is std_logic_vector of length 9, so you can't make assignment like this.
I'm not entirely sure what you are trying to achieve. If you want to assign '0' & d to some part of a vector, you can write for example
count(1 downto 0) <= '0' & d
If d is supposed to be equal size of counter, then change it's size in entity declaration.
I am rather new (3 weeks) to VHDL, and I am having a problem in my latest assignment, which involves implementing overflow checking in a simple 4-bit adder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity add_sub_4bit is
Port ( a : in STD_LOGIC_VECTOR(3 downto 0);
b : inout STD_LOGIC_VECTOR(3 downto 0);
sel: in STD_LOGIC );
--sum : inout STD_LOGIC_VECTOR(3 downto 0)
end add_sub_4bit;
architecture Behavioral of add_sub_4bit is
signal localflow : STD_LOGIC;
signal localsum : STD_LOGIC_VECTOR (3 downto 0);
begin
localsum <= a + b when sel = '1'
else
a - b;
process(a,b,localsum) begin
if a(3) = '0' AND b(3) = '0' AND localsum(3) = '1' then
localflow <= '1';
elsif a(3) = '1' AND b(3) = '1' AND localsum(3) = '0' then
localflow <='1';
else
localflow <='0';
end if;
end process;
end Behavioral;
Now, the test cases are as such:
A=5, B=-3, giving 0 to sel adds them, 1 subtracts.
A=6, B=2, working much the same.
Now, given that the numbers are signed, of course, they are two's complement numbers, so is the result. However, I can only detect overflow in a case of adding 6 (0110) and 2 (0010), giving out -8 (1000), which is obviously an overflow case in 4-bit. But, when doing 5 -(-3), the result is much the same, 1000, but since I have given numbers of two different signs, I cannot detect overflow using my method.
My teacher has suggested that we change the sign of B depending on the value of sel - I tried something like making b <= b+"1000" based on that but that didn't help, and I don't know of other ways, being very new to the language. What can I do to get a proper program? Thank you.
Firstly:
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Don't do that. Especially if you want the numbers to be signed. Normal to use is:
use IEEE.numeric_std.all;
After that, you should cast the std_logic_vector to the wanted data type, e.g. 'signed', for the correct arithmetic.
Secondly, don't use inout. VHDL is not so good with bidirectional assignments. Either use in or out.
So combining the above, you could do (n.b. not the best code):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity add_sub_4bit is
Port (
a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
sel: in STD_LOGIC;
sum : out STD_LOGIC_VECTOR(3 downto 0);
overflow : out std_logic
);
end add_sub_4bit;
architecture Behavioral of add_sub_4bit is
signal localflow : STD_LOGIC;
signal locala, localb, localsum : signed(4 downto 0); -- one bit more then input
signal sumout : std_logic_vector(4 downto 0);
begin
locala <= resize(signed(a), 5);
localb <= resize(signed(b), 5);
localsum <= locala + localb when sel = '1' else locala - localb;
-- overflow occurs when bit 3 is not equal to the sign bit(4)
localflow <= '1' when localsum(3) /= localsum(4) else '0';
-- convert outputs
sumout <= std_logic_vector(localsum);
--outputs
sum <= sumout(4)&sumout(2 downto 0);
overflow <= localflow;
end Behavioral;
You can test this using a testbench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity add_sub_4bit_tb is
end add_sub_4bit_tb;
architecture Behavioral of add_sub_4bit_tb is
signal sel : std_logic_vector(0 downto 0);
signal a, b, sum : std_logic_vector(3 downto 0);
begin
uut: entity work.add_sub_4bit
port map (a, b, sel(0), sum);
test: process
begin
for sel_o in 0 to 1 loop
sel <= std_logic_vector(to_signed(sel_o, 1));
for a_o in -8 to 7 loop
a <= std_logic_vector(to_signed(a_o, 4));
for b_o in -8 to 7 loop
b <= std_logic_vector(to_signed(b_o, 4));
wait for 1 ns;
end loop;
end loop;
end loop;
wait;
end process;
end Behavioral;