I am trying to make set&load d-flip flop code(synch) but it keeps giving me count <= '0' & d; it has 2 elements but must have 9 elements error.Thanks in advance
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity syn is
port (
clk : in std_logic;
rst_n : in std_logic;
d : in std_logic;
ld : in std_logic;
q : out std_logic_vector(7 downto 0);
co : out std_logic);
end syn;
architecture rtl of syn is
signal count : std_logic_vector(8 downto 0);
begin
co <= count(8);
q <= count(7 downto 0);
process (clk)
begin
if (clk'event and clk = '1') then
if (rst_n = '0') then
count <= (others => '0'); -- sync reset
elsif (ld = '1') then
count <= '0' & d; -- sync load
else
count <= count + 1; -- sync increment
end if;
end if;
end process;
end rtl;
Input d is std_logic, so '0' & d is 2 bit vector. Count is std_logic_vector of length 9, so you can't make assignment like this.
I'm not entirely sure what you are trying to achieve. If you want to assign '0' & d to some part of a vector, you can write for example
count(1 downto 0) <= '0' & d
If d is supposed to be equal size of counter, then change it's size in entity declaration.
Related
I've been asked at the university to make a 4-bit bidirectional shift register. I did it first this way:
-- bidirektionale shift register mit data-load und serielle(R/L) output
library ieee;
use ieee.std_logic_1164.all;
entity bi_shift_reg is
port( din: in std_logic_vector(3 downto 0);
set, n_reset: in std_logic;
sR, sL: in std_logic; -- Shift-Right/Shift-Left
data_load: in std_logic;
clk: in std_logic;
dout: inout std_logic_vector(3 downto 0);
s_dout_R: out std_logic; -- Serial Shift-Right output
s_dout_L: out std_logic -- Serial Shift-Left output
);
end bi_shift_reg;
architecture arch of bi_shift_reg is
begin
process(clk,set,n_reset)
begin
-- reset (low aktiv)
if n_reset = '0' then dout <= "0000";
-- set
elsif set = '1' then dout <= "1111";
-- data-load
elsif(rising_edge(clk) and data_load = '1') then
s_dout_R <= din(0);
s_dout_L <= din(3);
dout <= din;
-- shift right
elsif(rising_edge(clk) and sR = '1') then
s_dout_R <= din(0);
dout(2 downto 0) <= dout(3 downto 1);
-- shift left
elsif(rising_edge(clk) and sL = '1') then
s_dout_L <= din(3);
dout(3 downto 1) <= dout(2 downto 0);
end if;
end process;
end arch;
but then I heard that I needed to use my previous coded D-Flipflop as a component for the shift register. So my question is: since I have new inputs (data_load,shift_left and shift_right) and outputs(Serial Shift-Right, Serial Shift-Left) how can I add them in my code along with the d-ff component? is it possible to use a component and process together ?
This is my d-ff code with asynchronous activ-low reset and asynchronous set:
library ieee;
use ieee.std_logic_1164.all;
entity d_flipflop is
port( d, clk, set, n_reset: in std_logic;
q, qn: out std_logic
);
end d_flipflop;
architecture arch of d_flipflop is
begin
process(clk,set,n_reset)
variable temp: std_logic; -- zwischenergebniss
begin
if n_reset = '0' then
temp := '0';
elsif set = '1' then
temp := '1';
elsif rising_edge(clk) then
temp := d;
end if;
q <= temp;
qn <= not temp;
end process;
end arch;
How can I use my flipflop to achieve the same result as the code for the shift-register ?
Thank you in advance for your answers :D
After several good questions in the comment track by the OP, it is reasonable to post some design that can serve as an example for a solution.
Please note, that there was not any precise specification of the intended operation, e.g. what is priority between different inputs, and how should timing be for outputs, so the code below is provided with the intention of showing some VHDL structures that may works as a template for further update by the OP.
--###############################################################################
-- d_flipflop
library ieee;
use ieee.std_logic_1164.all;
entity d_flipflop is
port(d, clk, set, n_reset : in std_logic;
q, qn : out std_logic
);
end d_flipflop;
architecture arch of d_flipflop is
begin
process(clk, set, n_reset)
variable temp : std_logic; -- zwischenergebniss
begin
if n_reset = '0' then
temp := '0';
elsif set = '1' then
temp := '1';
elsif rising_edge(clk) then
temp := d;
end if;
q <= temp;
qn <= not temp;
end process;
end arch;
--###############################################################################
-- bi_shiftReg_ff
library ieee;
use ieee.std_logic_1164.all;
entity bi_shiftReg_ff is
port(din : in std_logic_vector(3 downto 0);
set, n_reset : in std_logic;
sR, sL : in std_logic; -- Shift-Right/Shift-Left
data_load : in std_logic;
clk : in std_logic;
dout : out std_logic_vector(3 downto 0);
s_dout_R : out std_logic; -- Shift-Right output
s_dout_L : out std_logic -- Shift-Left output
);
end bi_shiftReg_ff;
architecture arch of bi_shiftReg_ff is
-- FF component
component d_flipflop is
port(d, clk, set, n_reset : in std_logic;
q, qn : out std_logic
);
end component;
-- FF data input
signal d : std_logic_vector(3 downto 0);
-- FF data output
signal q : std_logic_vector(3 downto 0);
signal qn : std_logic_vector(3 downto 0); -- Unused, but included for completness
begin
-- Combinatorial process, thus making gates only
process (all)
begin
-- data-load
if (data_load = '1') then
d <= din;
-- shift right; priority over shift left
elsif (sR = '1') then
d <= '0' & q(q'left downto 1); -- Discard right-most bit in the right shift
-- shift left
elsif (sL = '1') then
d <= q(q'left - 1 downto 0) & '0'; -- Discard left-most bit in the left shift
end if;
end process;
-- State held in FFs
GEN_REG : for i in 0 to 3 generate
REGX : d_flipflop port map
(d(i), clk, set, n_reset, q(i), qn(i));
end generate;
-- Outputs drive
dout <= q;
s_dout_R <= q(q'right); -- Bit 0, but shown with VHDL attributes
s_dout_L <= q(q'left); -- Bit 3, --||--
end arch;
--###############################################################################
-- EOF
How can I implement Division and Multiplication manually in VHDL? That is; using Left & Right Shift and without the need for numeric_std (If possible).
A possible soulution:
library ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Shifter is
generic(
num_length : integer := 32
);
port(
EN : in std_logic;
clk : in std_logic;
number : in std_logic_vector((num_length - 1) downto 0);
dir : in std_logic;
result : out std_logic_vector((num_length - 1) downto 0));
end Shifter;
architecture Beh of Shifter is
signal temp : std_logic_vector((num_length - 1) downto 0);
begin
result <= std_logic_vector(temp);
process(EN, clk) is
begin
if EN = '0' then
temp <= (OTHERS => '0');
elsif rising_edge(clk) then
case dir is
when '0' => temp <= '0' & number((num_length - 2) downto 0);
when '1' => temp <= number((num_length - 2) downto 0) & '0';
end case;
end if;
end process;
end Beh;
Every clk cycle the position increases/decreases (depends on dir setting)
It can also be released with loops so that the module can increase/decrease more than one bit at a cycle.
Important: It is only possible to increase/decrease by the power of 2 (2,4,8,16,32,...) with shifting
I want to make a 4-Bit Adder and Subtractor with VHDL
I have created 1-Bit Full-Adder , XOR Gate ( for Subtract ) and a 4-Bit Adder as shown below :
Full-Adder :
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY FullAdder_1_Bit IS
PORT(
X, Y : IN STD_LOGIC;
CIn : IN STD_LOGIC;
Sum : OUT STD_LOGIC;
COut : OUT STD_LOGIC
);
END FullAdder_1_Bit;
ARCHITECTURE Behavier OF FullAdder_1_Bit IS
BEGIN
Sum <= X XOR Y XOR CIn;
COut <= (X AND Y) OR (X AND CIn) OR (Y AND CIn);
END Behavier;
XOR Gate :
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY XORGate IS
PORT(
X1, X2 : IN STD_LOGIC;
Y : OUT STD_LOGIC
);
END XORGate;
ARCHITECTURE Declare OF XORGate IS
BEGIN
Y <= X1 XOR X2;
END Declare;
4-Bit Adder :
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Adder_4_Bit IS
PORT(
A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Mode : IN STD_LOGIC;
Sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COut : OUT STD_LOGIC
);
END Adder_4_Bit;
ARCHITECTURE Structure OF Adder_4_Bit IS
COMPONENT FullAdder_1_Bit IS
PORT(
X, Y : IN STD_LOGIC;
CIn : IN STD_LOGIC;
Sum : OUT STD_LOGIC;
COut : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT XORGate IS
PORT(
X1, X2 : IN STD_LOGIC;
Y : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL COut_Temp : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL XB : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
B_0 : XORGate PORT MAP(Mode, B(0), XB(0));
B_1 : XORGate PORT MAP(Mode, B(1), XB(1));
B_2 : XORGate PORT MAP(Mode, B(2), XB(2));
B_3 : XORGate PORT MAP(Mode, B(3), XB(3));
SUM_0 : FullAdder_1_Bit
PORT MAP (A(0), XB(0), Mode, Sum(0), COut_Temp(0));
SUM_1 : FullAdder_1_Bit
PORT MAP (A(1), XB(1), COut_Temp(0), Sum(1), COut_Temp(1));
SUM_2 : FullAdder_1_Bit
PORT MAP (A(2), XB(2), COut_Temp(1), Sum(2), COut_Temp(2));
SUM_3 : FullAdder_1_Bit
PORT MAP (A(3), XB(3), COut_Temp(2), Sum(3), COut);
END;
and in my Main Codes , i have used those ( like Test-Bench ! ) :
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.ALL;
ENTITY Add_AND_Sub IS
END Add_AND_Sub;
ARCHITECTURE Declare OF Add_AND_Sub IS
COMPONENT Adder_4_Bit IS
PORT(
A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Mode : IN STD_LOGIC;
Sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COut : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL A, B : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL Mode : STD_LOGIC;
SIGNAL As, Bs, E, AVF : STD_LOGIC;
SIGNAL XA, XB, Sum : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
Add : Adder_4_Bit
PORT MAP(XA, XB, Mode, Sum, E);
PROCESS(A, B, Mode)
BEGIN
As <= A(4);
Bs <= B(4);
XA <= A(3 DOWNTO 0);
XB <= B(3 DOWNTO 0);
CASE Mode IS
WHEN '0' =>
IF ((As XOR Bs) = '1') THEN
Mode <= '1';
XA <= Sum;
AVF <= '0';
IF (E = '1') THEN
IF (XA = "0000") THEN
As <= '0';
END IF;
ELSE
XA <= (NOT XA) + "0001";
As <= NOT As;
END IF;
ELSE
XA <= Sum;
END IF;
WHEN '1' =>
IF ((As XOR Bs) = '1') THEN
Mode <= '0';
XA <= Sum;
AVF <= E;
ELSE
AVF <= '0';
XA <= Sum;
IF (E = '1') THEN
IF (XA = "0000") THEN
As <= '0';
END IF;
ELSE
XA <= (NOT XA) + "0001";
As <= NOT As;
END IF;
END IF;
WHEN Others =>
--
END CASE;
END PROCESS;
END Declare;
The main scenario is to Model this algorithm :
but now i want to have output in XA and As
I Should use registers shown in algorithm such as "E" and "AVF"
there is one question :
we know port maps are continuously connected , so when i change Mode Value , Result ( Sum ) must change , is it True ?!
I have tried this code but i cant get output in XA , and there is no True result for sum values , i know there is some problem in my main code ( Process ) , but i cant find problems
please check that codes and tell me what goes wrong !
Edit :
Im using ModelSim and its simulation for testing my code , first i force values of "A", "B" and "Mode" then run to get result and wave
thanks ...
Your testbench add_and_sub makes no assignments to it's a and b, they're default values are all 'U's.
What do you expect when your inputs to adder_4_bit are undefined?
Look at the not_table, or_table, and_table and xor_table in the body of the std_logic_1164 package.
Also to be a Minimal, Complete, and Verifiable example your readers need both expected and actual results.
If you're actually simulating the testbench I'd expect it consume no simulation time and after some number of delta cycles during initialization show sum and e chock full of 'U's.
I haven't personally modified your testbench to determine if your adder_4_bit works, but if you provide it with valid stimulus you can debug it. It can be helpful to consume simulation time and use different input values.
Adding a monitor process to add_and_sub:
MONITOR:
process (sum)
function to_string(inp: std_logic_vector) return string is
variable image_str: string (1 to inp'length);
alias input_str: std_logic_vector (1 to inp'length) is inp;
begin
for i in input_str'range loop
image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
end loop;
-- report "image_str = " & image_str;
return image_str;
end;
begin
report "sum = " & to_string(sum);
end process;
gives:
fourbitadder.vhdl:174:10:#0ms:(report note): sum = uuuu
one event on sum.
Add a process to cause events on a and 'b`:
STIMULUS:
process
begin
a <= "00000" after 10 ns;
b <= "00000" after 10 ns;
wait for 20 ns;
wait;
end process;
and we get:
(clickable)
We find we get an event on a and b but sum didn't change.
And the reason why is apparent in the case statement in the process. The default value of mode is 'U', and the case statement has choices for 0, 1 and:
when others =>
--
end case;
And the others choice results in no new value in mode.
Why nothing works can be discovered by reading the source of the body for package std_logic_1164, the xor_table, and_table, or_table. With mode = 'U' all your combinatorial outputs will be 'U'.
And to fix this you can assign a default value to mode where it is declared in the testbench:
signal mode : std_logic := '0';
With mode defined as a valid choice resulting in some action we note xa is now never defined causing the same issue:
(clickable)
And this is a problem in the process:
process(a, b, mode)
begin
as <= a(4);
bs <= b(4);
xa <= a(3 downto 0);
xb <= b(3 downto 0);
case mode is
when '0' =>
if ((as xor bs) = '1') then
mode <= '1';
xa <= sum;
avf <= '0';
if (e = '1') then
if (xa = "0000") then
as <= '0';
end if;
else
xa <= std_logic_vector(unsigned(not xa) + unsigned'("0001"));
as <= not as;
end if;
else
xa <= sum;
end if;
when '1' =>
if ((as xor bs) = '1') then
mode <= '0';
xa <= sum;
avf <= e;
else
avf <= '0';
xa <= sum;
if (e = '1') then
if (xa = "0000") then
as <= '0';
end if;
else
xa <= std_logic_vector(unsigned(not xa) + unsigned'("0001"));
as <= not as;
end if;
end if;
when others =>
--
end case;
Notice there are three places where xa is assigned, with no simulation time between them. There's only one projected output waveform value for any simulation time. A later assignment in the same process will result in the later value being assigned, in this case sum, which is all 'U's.
So how do you solve this conundrum? There are two possibilities. First you could not try and do algorithmic stimulus generation, assigning input to add explicitly with wait statements between successive assignments of different values. You can also insert delays between successive assignments to the same signal in the existing process, which requires a substantial re-write.
On a positive note the adder_4_bit and full_adder_1bit look like they should work. The problem appears to be all in the testbench.
I made some changes
I made a ALU unit as :
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.ALL;
ENTITY ALU IS
PORT(
--Clk : IN STD_LOGIC;
A, B : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
Sel : IN STD_LOGIC;
AOut : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
AsO : OUT STD_LOGIC
);
END ALU;
ARCHITECTURE Declare OF ALU IS
COMPONENT Adder_4_Bit IS
PORT(
A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Mode : IN STD_LOGIC;
Sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COut : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL As, Bs, E, AVF : STD_LOGIC;
SIGNAL XA, XB, Sum : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL Mode : STD_LOGIC;
BEGIN
Add : Adder_4_Bit
PORT MAP(XA, XB, Mode, Sum, E);
PROCESS
BEGIN
As <= A(4);
Bs <= B(4);
XA <= A(3 DOWNTO 0);
XB <= B(3 DOWNTO 0);
CASE Sel IS
WHEN '0' =>
IF ((As XOR Bs) = '1') THEN
Mode <= '1';
AVF <= '0';
WAIT ON Sum;
IF (E = '1') THEN
IF (Sum = "0000") THEN
As <= '0';
END IF;
ELSE
Sum <= (NOT Sum) + "0001";
As <= NOT As;
END IF;
ELSE
Mode <= '0';
WAIT ON Sum;
END IF;
AOut <= Sum;
AsO <= As;
WHEN '1' =>
IF ((As XOR Bs) = '1') THEN
Mode <= '0';
WAIT ON Sum;
AVF <= E;
ELSE
Mode <= '1';
WAIT ON Sum;
AVF <= '0';
IF (E = '1') THEN
IF (Sum = "0000") THEN
As <= '0';
END IF;
ELSE
Sum <= (NOT Sum) + "0001";
As <= NOT As;
END IF;
END IF;
AOut <= Sum;
AsO <= As;
WHEN Others =>
--
END CASE;
END PROCESS;
END Declare;
and A Test Bench like this :
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.ALL;
ENTITY ALU_Test_Bench IS
END ALU_Test_Bench;
ARCHITECTURE Declare OF ALU_Test_Bench IS
COMPONENT ALU IS
PORT(
--Clk : IN STD_LOGIC;
A, B : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
Sel : IN STD_LOGIC;
AOut : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
AsO : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL Xs, S : STD_LOGIC;
SIGNAL X, Y, O : STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
ALU_PM : ALU PORT MAP(X, Y, S, O, Xs);
Main_Process : PROCESS
BEGIN
WAIT FOR 100 ns;
X <= "00010";
Y <= "11011";
S <= '0';
WAIT FOR 30 ns;
S <= '1';
WAIT FOR 30 ns;
WAIT FOR 100 ns;
X <= "01110";
Y <= "10011";
S <= '0';
WAIT FOR 30 ns;
S <= '1';
WAIT FOR 30 ns;
WAIT FOR 100 ns;
X <= "10011";
Y <= "11111";
S <= '0';
WAIT FOR 30 ns;
S <= '1';
WAIT FOR 30 ns;
END PROCESS;
END Declare;
As i say , i want to model the algorithm i posted in first post
there is some problem ...
for example when i simulate and run test bench , there is no output value in O and Xs !
I know the problem is in ALU and Test Bench
I changed ALU many times and tested many ways but all times some things goes wrong !
If you want to code that algorithm , which units you will create or at all what will you create ?! and how will you code that ?!
thanks for your help ...
I'm trying to make a VHDL code for 4-bit universal shift register, where I want to load 4 bits and choose the shift-operation from the ctrl. I don't know how to implement a clock divider to run the outputs on a FPGA.
Here is my code so far:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity shift_register is
generic(N : integer := 4);
port(
clk, reset : in std_logic;
ctrl : in std_logic_vector(1 downto 0);
d : in std_logic_vector((N-1) downto 0);
q : out std_logic_vector((N-1) downto 0)
);
end shift_register;
architecture Behavioral of shift_register is
signal r_reg : std_logic_vector((N-1) downto 0);
signal r_next : std_logic_vector((N-1) downto 0);
begin
process(clk, reset)
begin
if(reset = '1') then
r_reg <= (others => '0');
elsif(clk'event and clk = '1') then
r_reg <= r_next;
end if;
end process;
with ctrl select
r_next <=
r_reg when "00", --do nothing
r_reg(N-2 downto 0) & d(0) when "01", --shift left
d(N-1) & r_reg(N-1 downto 1)when "10", --shift right
d when others; --load
q <= r_reg;
end Behavioral;
Divider code template with enable asserted a single cycle every RATIO clock cycles:
library ieee;
use ieee.numeric_std.all;
architecture syn of mdl is
constant RATIO : natural := 10;
signal prescale : std_logic_vector(9 downto 0); -- Scale to fit RATIO - 1
signal enable : std_logic;
begin
process (clk, reset) is
begin
if reset = '1' then
enable <= '0';
prescale <= std_logic_vector(to_unsigned(RATIO - 1, prescale'length));
elsif rising_edge(clk) then
if unsigned(prescale) = 0 then
enable <= '1';
prescale <= std_logic_vector(to_unsigned(RATIO - 1, prescale'length));
else
enable <= '0';
prescale <= std_logic_vector(unsigned(prescale) - 1);
end if;
end if;
end process;
end architecture;
I'm trying to make a 8-bit shift register using D flipflop.
The problem is that when simulating it takes two clock rising edges for the register to shift, one for the D input to change, the other for the Q to change. I don't know why.
entity Registry_8 is
port (input : in std_logic;
output : out std_logic;
clk : in std_logic;
clear : in std_logic;
load : in std_logic;
LR : in std_logic;
pIn : in std_logic_vector (7 downto 0);
pOut : out std_logic_vector (7 downto 0);
shift : in std_logic);
end Registry_8;
architecture Behavioral of Registry_8 is
component D_flipflop
port(D, clk, clear, preset : in std_logic;
Q, Q_b : out std_logic);
end component;
signal D, Q : std_logic_vector (7 downto 0);
begin
GEN_FLIP :
for i in 0 to 7 generate
D_i : D_flipflop port map(clk => clk, preset => '0', clear => clear, D => D(i), Q => Q(i));
end generate GEN_FLIP;
process (clk, load, LR, shift)
begin
if (load = '1')
then D <= pIn;
end if;
if (clk'event and clk = '1' and shift = '1')
then
if (LR = '0')
then D(7 downto 0) <= Q(6 downto 0) & input;
output <= Q(7);
else
D(7 downto 0) <= input & Q(7 downto 1);
output <= Q(0);
end if;
end if;
end process;
pOut <= Q;
end Behavioral;
In the process, there is clock edge sensitive condition with the expression:
clk'event and clk = '1'
The process thereby implements an additional level of sequential logic (flip
flops), but you probably wanted to create a process for purely combinatorial
design, like:
process (all) is
begin
if (load = '1') then
D <= pIn;
end if;
if shift = '1' then
if (LR = '0') then
D(7 downto 0) <= Q(6 downto 0) & input;
output <= Q(7);
else
D(7 downto 0) <= input & Q(7 downto 1);
output <= Q(0);
end if;
end if;
end process;
Note that VHDL-2008 all is used as sensitivity list above, to automatically
include all signals used in a process for combinatorial design.