I want to build a full adder in VHDL and read the result from one of the pins.
entity main is
port (foo: out std_logic);
end entity main;
Given this code, how do I map foo to a real pin on my FPGA?
Here are the details of the FPGA I'm using:
Manufacturer: Xilinx
Family: Spartan 3e
Device: XC3S500E
Package:FT256
In Xilinx ISE, add your file to the project; it should be automatically set as the top level entity. In the 'Processes' panel (typically near the bottom left), expand 'User Constraints' and double click 'I/O Pin Planning (PlanAhead) - Pre-Synthesis'. This opens the PlanAhead pin planning tool. Using this, you can easily drag your port onto a pin of your device. Saving in this program should create a 'constraints' (.ucf) file. You can also edit this file manually. ISE will use this constraints file when compiling your FPGA.
Related
I am writing a code for spi slave and wishbone bus. The issue is that the testbench file shows all the signals correctly (the signals and ports that are used in testbench) but when I am trying to check the state machine in the main code it shows nothing red line. I tried to define an output port and assign the state to it, it did not work because I don't know how to make an output port as a string because the state is like this
TYPE wb_state_t IS
(
WB_IDLE,
WB_WRITE,
WB_READ,
WB_FINISH
);
SIGNAL wb_state : wb_state_t;
I want to assign wb_state to an output port so I can check the state in the testbench.
How can I do that?
As you read in the comments, I only needed to make a simple package and put the state machine cases in it and call it in both the top level and the testbench files.
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package wb_state_machine is
TYPE wb_state_t IS
(
WB_IDLE,
WB_WRITE,
WB_READ,
WB_FINISH
);
end package;
lot of simulator are able to display internal signal. for instance on vivado or Questa you can click on the design name when you are on the waves page. Then you take your signal and slide it on waves and rerun simulation
I completed Anton Potočniks' introductory guide to the red pitaya board and I am now able to send commands from the linux machine running on the SoC to its FPGA logic.
I would like to further modify the project so that I can control the phase of the signal that is being transmitted via the red pitayas' DAC. Some pins (from 7 down to 1) of the first GPIO port were still unused so I started setting them from within the OS and used the red pitaya's LEDs to confirm that they were being set without interfering with the functionality of Anton Potočnik's "high bandwidth averager".
I then set the DDS_compilers' to Phase Offset Programmability to "streaming" mode so that it can be configured on the fly using the bits that are currently controling the red pitaya's LEDs. I used some slices to connect my signals to the AXI4-Stream Constant IP core, which in turn drives the DDS compiler.
Unfortunately the DAC is just giving me a constant output of 500 mV.
I created a new project with a testbench for the DDS compiler, because synthesis takes a long time and doesn't give me much insight into what is happening.
Unfortunately all the output signals of the DDS compiler are undefined.
My question:
What am I doing wrong and how can I proceed to control DACs' phase?
EDIT1; here is my test bench
The IP core is configured as follows, so many of the control signals that I provided should not be required:
EDIT2; I changed declarations of the form m_axis_data_tready => '0' to m_axis_phase_tready => m_axis_phase_tready_signal. I also took a look at the wrapper file called dds_compiler_0.vhd and saw that it treats both m_axis_phase_tready and m_axis_data_tready as inputs.
My simulation results remained unchanged...
My new test bench can be found here.
EDIT3: Vivado was just giving me the old simulation results - creating a new testbench, deleting the file under <project_name>.sim/sim_1/behav/xsim/simulate.log and restarting vivado solved this problem.
I noticed that the wrapper file (dds_compiler_0.vhd) only has five ports:
aclk (in)
s_axis_phase_tvalid (in)
s_axis_phase_tdata (in)
m_axis_data_tvalid (out)
and m_axis_data_tdata (out)
So I removed all the unnecessary control signals and got a new simulation result, but I am still not recieving any useful output from the dds_compiler:
The corresponding testbench can be found here.
I also don't get any valid output when I include the control signals.
The corresponding testbench can be found here.
Looks like m_axis_data_tready is not connected. No data will come out unless that's asserted.
Basically, this problem is related to mapping the toplevel IO's of either verilog or vhdl to the unused pins of a Xilinx FPGA.
Xilinx's old FPGA compiler, "ISE", used to give you a report of the "pin assignments" that the compiler was able to map to the bitfile, once the compiler was finished generating the FPGA binary file for upload.
However, with Xilinx's Vivado FPGA compiler, I have no idea where this report is located...
Does anybody know where to find the report or what the FPGA compiler actually mapped to the pins of the FPGA after finishing the compilation?
Basically, I want to see that Vivado accepted the IO's that I listed in the Xilinx Constraint file and was able to finishing mapping them to the FPGA pins in the Compiler output bitsteam file.
If you haven't warnings or errors relative to your pins after generating bitstream, Vivado has accepted your pinout.
You can have a view of your pins in Vivado :
- Open your implemented design via the left panel
- Layout -> IO planning (on the top bar)
I have a circuit created by VHDL code in Quartus II. There I have a state machine. I chose the type of encoding: one-hot. I have 9 states and so I should have 9 flipflops.
Is it possible to watch how Quartus implements them on scheme? I can see only state table.
Another question is how to use the outputs of these flipflops. I need to connect them to leds but I don't know how to find them.
If it's necessary I will add my code.
You can check your state machine in Quartus this way: "Tools" -> "Netlist Viewers" -> "State Machine Viewer"
You have to connect your LED output port(s) of your top level entity to the pins on your FPGA. You have to look up in the user manual of your FPGA which pins are used for LEDs. In Quartus you can choose "Assigments" => "Assigment Editor"
Example:
In QSYS I have an ADC, PLL and an Avalon-MM Read Master to access the internal ADC of the Altera Max10. The control and user interface of the Read Master are exported.
Now I struggle to setup the control interface to access the ADC channels. Mainly following signals:
control_fixed_location
control_read_base
control_read_length
The interface description is:
The block diagram for the Read Master is:
Questions:
- How do I need to set the control signals to access the ADC channel x?
- Where can I find the base address for the ADC implemented in QSYS?
Attached is the quartus archive. Maybe someone can give me an example to simulate this interface in ModelSim.
Thanks in advance!
I have an answer to your second question. I am struggling myself with the first question.
Where can I find the base address for the ADC implemented in QSYS?
I know two methods to find the base and end address of a component.
One is to open the System Contents view (standard) and scroll to the right side .
I am not permited to embed images yet.
There you see a row named Base and End. Here you can find the addresses.
The second method is to open the Address Map. Should be located in the same column as System Contents, or you can select View in the top left corner and select it there.
Have a look. You should be able to find it yourself with this information.
What i use when i am searching for examples or prebuild designs is the altera website. Here a link for you https://cloud.altera.com/devstore/platform/
Probably you like this one: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max-10/ug_m10_adc.pdf
The configuration is complete in QSYS? Like selecting channels and Sequencer in your ADC Block. Selecting the right input clocks and the right frequencies?
You wrote:
In QSYS I have an ADC, PLL and an Avalon-MM Read Master to access the internal ADC of the Altera Max10. The control and user interface of the Read Master are exported.
Have you created a clock for your PLL? When i want to simulate a clock signal for a QSYS system i export the clock signals and define the wanted clock in an additional file.
When you go one step further and include a nios2 processor i recommend to have a look at the altera_modular_adc.c file.
*edit
If you haven't assigned any base addresses there is a function in QSYS which does the job for you.
In System (Same column as File) -> Assign Base Addresses