I have a circuit created by VHDL code in Quartus II. There I have a state machine. I chose the type of encoding: one-hot. I have 9 states and so I should have 9 flipflops.
Is it possible to watch how Quartus implements them on scheme? I can see only state table.
Another question is how to use the outputs of these flipflops. I need to connect them to leds but I don't know how to find them.
If it's necessary I will add my code.
You can check your state machine in Quartus this way: "Tools" -> "Netlist Viewers" -> "State Machine Viewer"
You have to connect your LED output port(s) of your top level entity to the pins on your FPGA. You have to look up in the user manual of your FPGA which pins are used for LEDs. In Quartus you can choose "Assigments" => "Assigment Editor"
Example:
Related
I completed Anton Potočniks' introductory guide to the red pitaya board and I am now able to send commands from the linux machine running on the SoC to its FPGA logic.
I would like to further modify the project so that I can control the phase of the signal that is being transmitted via the red pitayas' DAC. Some pins (from 7 down to 1) of the first GPIO port were still unused so I started setting them from within the OS and used the red pitaya's LEDs to confirm that they were being set without interfering with the functionality of Anton Potočnik's "high bandwidth averager".
I then set the DDS_compilers' to Phase Offset Programmability to "streaming" mode so that it can be configured on the fly using the bits that are currently controling the red pitaya's LEDs. I used some slices to connect my signals to the AXI4-Stream Constant IP core, which in turn drives the DDS compiler.
Unfortunately the DAC is just giving me a constant output of 500 mV.
I created a new project with a testbench for the DDS compiler, because synthesis takes a long time and doesn't give me much insight into what is happening.
Unfortunately all the output signals of the DDS compiler are undefined.
My question:
What am I doing wrong and how can I proceed to control DACs' phase?
EDIT1; here is my test bench
The IP core is configured as follows, so many of the control signals that I provided should not be required:
EDIT2; I changed declarations of the form m_axis_data_tready => '0' to m_axis_phase_tready => m_axis_phase_tready_signal. I also took a look at the wrapper file called dds_compiler_0.vhd and saw that it treats both m_axis_phase_tready and m_axis_data_tready as inputs.
My simulation results remained unchanged...
My new test bench can be found here.
EDIT3: Vivado was just giving me the old simulation results - creating a new testbench, deleting the file under <project_name>.sim/sim_1/behav/xsim/simulate.log and restarting vivado solved this problem.
I noticed that the wrapper file (dds_compiler_0.vhd) only has five ports:
aclk (in)
s_axis_phase_tvalid (in)
s_axis_phase_tdata (in)
m_axis_data_tvalid (out)
and m_axis_data_tdata (out)
So I removed all the unnecessary control signals and got a new simulation result, but I am still not recieving any useful output from the dds_compiler:
The corresponding testbench can be found here.
I also don't get any valid output when I include the control signals.
The corresponding testbench can be found here.
Looks like m_axis_data_tready is not connected. No data will come out unless that's asserted.
Basically, this problem is related to mapping the toplevel IO's of either verilog or vhdl to the unused pins of a Xilinx FPGA.
Xilinx's old FPGA compiler, "ISE", used to give you a report of the "pin assignments" that the compiler was able to map to the bitfile, once the compiler was finished generating the FPGA binary file for upload.
However, with Xilinx's Vivado FPGA compiler, I have no idea where this report is located...
Does anybody know where to find the report or what the FPGA compiler actually mapped to the pins of the FPGA after finishing the compilation?
Basically, I want to see that Vivado accepted the IO's that I listed in the Xilinx Constraint file and was able to finishing mapping them to the FPGA pins in the Compiler output bitsteam file.
If you haven't warnings or errors relative to your pins after generating bitstream, Vivado has accepted your pinout.
You can have a view of your pins in Vivado :
- Open your implemented design via the left panel
- Layout -> IO planning (on the top bar)
In QSYS I have an ADC, PLL and an Avalon-MM Read Master to access the internal ADC of the Altera Max10. The control and user interface of the Read Master are exported.
Now I struggle to setup the control interface to access the ADC channels. Mainly following signals:
control_fixed_location
control_read_base
control_read_length
The interface description is:
The block diagram for the Read Master is:
Questions:
- How do I need to set the control signals to access the ADC channel x?
- Where can I find the base address for the ADC implemented in QSYS?
Attached is the quartus archive. Maybe someone can give me an example to simulate this interface in ModelSim.
Thanks in advance!
I have an answer to your second question. I am struggling myself with the first question.
Where can I find the base address for the ADC implemented in QSYS?
I know two methods to find the base and end address of a component.
One is to open the System Contents view (standard) and scroll to the right side .
I am not permited to embed images yet.
There you see a row named Base and End. Here you can find the addresses.
The second method is to open the Address Map. Should be located in the same column as System Contents, or you can select View in the top left corner and select it there.
Have a look. You should be able to find it yourself with this information.
What i use when i am searching for examples or prebuild designs is the altera website. Here a link for you https://cloud.altera.com/devstore/platform/
Probably you like this one: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max-10/ug_m10_adc.pdf
The configuration is complete in QSYS? Like selecting channels and Sequencer in your ADC Block. Selecting the right input clocks and the right frequencies?
You wrote:
In QSYS I have an ADC, PLL and an Avalon-MM Read Master to access the internal ADC of the Altera Max10. The control and user interface of the Read Master are exported.
Have you created a clock for your PLL? When i want to simulate a clock signal for a QSYS system i export the clock signals and define the wanted clock in an additional file.
When you go one step further and include a nios2 processor i recommend to have a look at the altera_modular_adc.c file.
*edit
If you haven't assigned any base addresses there is a function in QSYS which does the job for you.
In System (Same column as File) -> Assign Base Addresses
I want to build a full adder in VHDL and read the result from one of the pins.
entity main is
port (foo: out std_logic);
end entity main;
Given this code, how do I map foo to a real pin on my FPGA?
Here are the details of the FPGA I'm using:
Manufacturer: Xilinx
Family: Spartan 3e
Device: XC3S500E
Package:FT256
In Xilinx ISE, add your file to the project; it should be automatically set as the top level entity. In the 'Processes' panel (typically near the bottom left), expand 'User Constraints' and double click 'I/O Pin Planning (PlanAhead) - Pre-Synthesis'. This opens the PlanAhead pin planning tool. Using this, you can easily drag your port onto a pin of your device. Saving in this program should create a 'constraints' (.ucf) file. You can also edit this file manually. ISE will use this constraints file when compiling your FPGA.
I am new to the Zedboard and am working up to transferring a complex hardware accelerator I currently have working on a regular FPGA board. Anyway I want to walk before I can run so have done the Zedboard speedway tutorials and am now toying around with small projects. My first of which being an simple adder accelerator:
-Send 2 numbers to the pl(programmable logic), to reg a and b
-the pl adds the numbers
-an interrupt to the PS(CPU) signals the computation has finished.
-In the ISR the PS reads the result from reg c
For this design I am using 3 registers (a,b,c) in the AXI interconnect, I have created the IP templates using CIP.
Basically though what is the best way send a control signal to enable the addition to the PL. So how should I signal to the PL adder that I have loaded the two numbers in reg a and b and now want to add them?
-Should I create a 1bit signal GPIO interconnect, add a 4th 1 bit control register to the IP? or is there a more 'stylish' way to do this by using the BUS2IPdata signals?
-Or is there another way to create custom PS to PL control enable signals?
Many thanks
Sam
Current idea:
-Build a switch in the user_logic HDL based on the BUS2IPWrCE, so when this is asserted to write to reg B I can then signal an enable signal to my adder? Or will I run into some concurrency issues with the data not being fully written straight away?
So to do this I have created the AXI perph using CIP, then modified the used_logic and two new ports, en and interrupt. Following these instructions I employed these external connections.http://www.programmableplanet.com/author.asp?section_id=2142&doc_id=264841
I then connected these two external connections to GPIO interfaces to provide the required functionality.
In your larger designs, it will be difficult to get performance using a GPIOs to control the scheduling of your accelerators. I suggest setting up FIFOs of command blocks between software and hardware.
For example, your peripheral could implement an AXI Stream slave, to receive commands from software, and an AXI Stream master, to send result indications back to software.
It can assert an interrupt to indicate that there are values in the response FIFO.
For higher performance, set up these FIFOs in DRAM and use AXI read/write masters in your peripheral.