In my VHDL code I have an error in sig_out_real <= X"00" & sig_in when sig_in(7)='0' else X"ff" & sig_in;.
I don't think it is a syntax error. But Quartus shows an error at that point.
I don`t understand why it's an error.
Can anyone provide information:
-- Error--
Error (10500): VHDL syntax error at S8BT16B.vhd(35) near text "when"; expecting ";"
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
use work.fft_package.all;
entity S8BT16B is
port(
clk_50 : in std_logic;
clk_baud : in std_logic;
main_reset : in std_logic;
enable : in std_logic;
sig_in : in signed (7 downto 0);
sig_out : out complex;
valid_output : out std_logic
);
end S8BT16B;
architecture Behavioral of S8BT16B is
type state is (idle,start);
signal state_reg, next_state_reg : state;
signal sig_out_real : signed(15 downto 0);
begin
state_change : process(clk_50, main_reset)
begin
if (main_reset = '1' or enable = '0') then
state_reg <= idle;
elsif (main_reset ='0' and enable = '1') then
state_reg <= next_state_reg;
end if;
end process;
S8BT16B_active : process(clk_baud, state_reg)
begin
if (state_reg = idle) then
sig_out_real <="0000000000000000";
sig_out <=(sig_out_real,"0000000000000000");
next_state_reg <= start;
valid_output <= '0';
elsif (state_reg = start and enable = '1') then
sig_out_real <= X"00" & sig_in when sig_in(7)='0' else X"ff" & sig_in;
sig_out <= (signed_converted_input, "0000000000000000");
next_state_reg <= idle;
valid_output <= '1';
end if;
end process;
end Behavioral;
You code does not present a Minimal, Complete, and Verifiable example.
The package fft_package presumably containing the type declaration for complex is not present.
The declaration for signed_converted_input is also not present.
A sequential conditional signal assignment statement is only available in VHDL-2008.
There's a good argument to be made that the Synopsys packages std_logic_arith and std_logic_signed are not compatible with IEEE Std 1076-2008's defined package std_logic_1164. It's possible they've been re-written to accomidate the new definitions of std_logic_vector and std_ulogic vector, although not if they work without -2008 compatibility, without some serious automagic on the part of ALDEC.
If passing a -2008 compatibility flag doesn't fix things for you the simplest thing you can do is replace the sequential conditional signal assignment statement with two simple signal assignment statements inside an if statement:
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
package fft_package is
type complex is record
sig_real: signed (15 downto 0);
sig_imaginary: signed (15 downto 0);
end record;
constant signed_converted_input: signed (15 downto 0) := (others => '0');
end package;
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use work.fft_package.all;
entity S8BT16B is
port(
clk_50: in std_logic;
clk_baud: in std_logic;
main_reset: in std_logic;
enable: in std_logic;
sig_in: in signed (7 downto 0);
sig_out: out complex;
valid_output: out std_logic
);
end S8BT16B;
architecture Behavioral of S8BT16B is
type state is (idle,start);
signal state_reg, next_state_reg: state;
signal sig_out_real: signed(15 downto 0);
begin
state_change:
process(clk_50, main_reset)
begin
if (main_reset = '1' or enable = '0') then
state_reg <= idle;
elsif (main_reset ='0' and enable = '1') then
state_reg <= next_state_reg;
end if;
end process;
S8BT16B_active:
process(clk_baud, state_reg)
begin
if state_reg = idle then
sig_out_real <= "0000000000000000";
sig_out <=(sig_out_real,"0000000000000000");
next_state_reg <= start;
valid_output <= '0';
elsif state_reg = start and enable = '1' then
-- sig_out_real <= X"00" & sig_in when sig_in(7)='0' else
-- X"ff" & sig_in;
if sig_in(7) = '0' then
sig_out_real <= X"00" & sig_in;
else
sig_out_real <= X"ff" & sig_in;
end if;
sig_out <= (signed_converted_input, "0000000000000000");
next_state_reg <= idle;
valid_output <= '1';
end if;
end process;
end Behavioral;
This code analyzes, elaborates and simulates (to show there are no length mismatches without regards to sig_in(7) = '0') while any claim to it's functionality is not made. The length looks right in the assignments to sig_out_real.
And of course without seeing the actual contents of your package fft_package claims to syntax and semantic validity can't be absolutely made (the faux package and your modified code are consistent with each other).
Related
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sqwaveGen is
port (
clk : in std_logic;
clk_out : out std_logic;
fall : in unsigned(7 downto 0);
reset : in std_logic;
rise : in unsigned(7 downto 0)
);
end entity;
architecture from_verilog of sqwaveGen is
signal count : unsigned(7 downto 0); -- Declared at design.sv:7
signal count_off : unsigned(7 downto 0); -- Declared at design.sv:7
signal count_on : unsigned(7 downto 0); -- Declared at design.sv:7
signal pos_or_neg : std_logic; -- Declared at design.sv:8
begin
clk_out <= pos_or_neg;
process (clk, reset) is
begin
if (not reset) = '1' then
count <= X"00";
count <= X"00";
pos_or_neg <= '1';
elsif rising_edge(clk) then
if (unsigned'("0000000000000000000000000000000") & pos_or_neg) = X"00000001" then
if Resize(count, 32) = (Resize(count_on, 32) - X"00000001") then
count <= X"00";
pos_or_neg <= '0';
else
count <= count + X"01";
end if;
else
if (unsigned'("0000000000000000000000000000000") & pos_or_neg) = X"00000000" then
if Resize(count, 32) = (Resize(count_off, 32) - X"00000001") then
count <= X"00";
pos_or_neg <= '1';
else
count <= count + X"01";
end if;
end if;
end if;
end if;
end process;
process (fall, rise) is
begin
count_on <= rise;
count_off <= fall;
end process;
end architecture;
You're trying to simulate a VHDL design with Icarus (iverilog) simulator, which is a Verilog simulator and does not support VHDL!
Use should use a simulator which supports VHDL, such as GHDL or Xilinx Vivado. Also save the file with ".vhd" or ".vhdl" extension.
I was trying to do a work and this error is boring me, i pass to a new project teste.vhdl and this keep happening, i need to have two barriers of clock one for input and another to output, to use timequest with combinational logic.
The 'and' is just a example.
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
ENTITY teste IS
PORT(
clock : in std_logic;
clear : in std_logic;
a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
s : out std_logic_vector(3 downto 0)
);
END teste;
ARCHITECTURE comportamento OF teste IS
signal a1,b1,s1 : std_logic_vector(3 downto 0);
begin
FF_in: process(clock.clear)
begin
if clear = '1' then
a1 <= "0000";
b1 <= "0000";
elsif clock'event and clock = '1' then
a1 <= a;
b1 <= b;
end if;
end process;
s1 <= a1 and b1;
FF_out: process(clock.clear)
begin
if clear = '1' then
s <= "0000";
elsif clock'event and clock = '1' then
s <= s1;
end if;
end process;
END comportamento;
You have used a . Rather than , in the process sensitivity list. Using a . Is trying to access a record field.
This is my code for converting binary to BCD in VHDL
library ieee;
use ieee.numeric_bit.all;
entity bin2bcd is
port (bin : in bit_vector(3 downto 0) := "0000";
clk : in bit;
bcdout : out bit_vector(4 downto 0) := "00000");
end bin2bcd;
architecture bin2bcdarch of bin2bcd is
begin
process(clk)
variable gt9 : bit;
variable temp : bit_vector(3 downto 0) := "0110";
variable bcdout_temp : bit_vector(4 downto 0);
begin
if clk'event and clk = '1' then
gt9 := bin(3) and(bin(2) or bin(1));
if gt9 = '1' then
bcdout_temp := ('0' & bin) + ('0' & temp);
else
bcdout_temp := ('0' & bin);
end if;
end if;
bcdout <= bcdout_temp;
end process;
end bin2bcdarch;
The problem is when i am trying to add the two bit_vector in the line
bcdout_temp := ('0' & bin) + ('0' & temp);
using "+" operator, that I get the error
(vcom-1581) No feasible entries for infix operator '+'.
Now, I looked in the web and most of the solutions are for when I use std_logic_vector.
The code works fine if I use std_logic_vector but not when I use bit_vector.
Is there any solution to the problem as to why I am getting the error?
You can add bit vectors if you use ieee.numeric_bit_unsigned.all which is part of VHDL-2008. The numeric_std package you're using does not define addition for bit vector.
If you find your old CAD lab software doesn't support numeric_bit_unsigned you can use type conversions, numeric_bit contains declarations for types signed and unsigned:
library ieee;
use ieee.numeric_bit.all;
entity bin2bcd is
port (bin : in bit_vector(3 downto 0) := "0000";
clk : in bit;
bcdout : out bit_vector(4 downto 0) := "00000");
end bin2bcd;
architecture bin2bcdarch of bin2bcd is
begin
process(clk)
variable gt9 : bit;
variable temp : unsigned(3 downto 0) := "0110"; -- was bit_vector
variable bcdout_temp : unsigned(4 downto 0); -- was bit vector
begin
if clk'event and clk = '1' then
gt9 := bin(3) and(bin(2) or bin(1));
if gt9 = '1' then
bcdout_temp := '0' & unsigned(bin) + ('0' & temp); -- type conversion
else
bcdout_temp := '0' & unsigned(bin); -- type conversion
end if;
end if;
bcdout <= bit_vector(bcdout_temp); -- type conversion
end process;
end bin2bcdarch;
Note temp can also be class constant instead of variable, it's not assigned other than an initial value.
From your comments using WARP2 to synthesis (presumably CPLDs) I recall that it was originally developed to use AHDL as input description and that support for VHDL and Verilog were an afterthought.
You're likely seeing limitations based on what VHDL constructs map to AHDL constructs that are supported for synthesis.
The way to deal with such limitations may be to describe troublesome parts of designs as a dataflow description:
entity bin2bcd is
port (
bin: in bit_vector(3 downto 0);
clk: in bit;
bcdout: out bit_vector(4 downto 0)
);
end entity bin2bcd;
architecture dataflow of bin2bcd is
signal bcdout_temp: bit_vector(4 downto 0);
begin
bcdout_temp(4) <= bin(3) and ( bin(2) or bin(1) ); -- gt9
bcdout_temp(3) <= not bcdout_temp(4) and bin(3); -- zero if gt9
bcdout_temp(2) <= ( bin(3) and bin(2) and bin(1)) or
(not bin(3) and bin(2));
bcdout_temp(1) <= ( bcdout_temp(4) and not bin(1)) or -- gt9 XOR bin(1)
(not bcdout_temp(4) and bin(1));
bcdout_temp(0) <= bin(0); -- doesn't change
REG5:
process (clk)
begin
if clk'event and clk = '1' then
bcdout <= bcdout_temp;
end if;
end process;
end architecture;
While there's no guarantee of this would work better (although likely) it also simulates as VHDL with a testbench:
library ieee;
use ieee.numeric_bit.all;
entity bin2bcd_tb is
end entity;
architecture foo of bin2bcd_tb is
signal bin: bit_vector(3 downto 0);
signal clk: bit;
signal bcdout: bit_vector(4 downto 0);
begin
DUT:
entity work. bin2bcd (dataflow)
port map (
bin => bin,
clk => clk,
bcdout => bcdout
);
CLOCK:
process
begin
wait for 5 ns;
clk <= not clk;
if now > 160 ns then
wait;
end if;
end process;
STIMULI:
process
begin
for i in 0 to 2 ** bin'length - 1 loop
bin <= bit_vector(to_unsigned(i, bin'length));
wait for 10 ns;
end loop;
wait;
end process;
end architecture;
And shows it gives the right results:
bin is displayed in decimal while bcdout is displayed in hex.
I'm trying to make a 8-bit Sequential Multiplier on Quartus II. I did all the simulations of all blocks, but one is showing error on the VWF simulation. The sum_reg block it's doing a infinite shift in a very small time interval.
In the "dark blue" part of waveform simulation, on o_DOUT, it's when the shift gones infinite until the MSB goes to the LSB. The image below shows what happens in the dark blue part of the simulation:
Someone know what's happen?
Below the code:
Sum register(where the simulation goes wrong):
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sum_register is
port (
i_DIN : in UNSIGNED(8 DOWNTO 0);
i_LOAD : in STD_LOGIC;
i_CLEAR : in STD_LOGIC;
i_SHIFT : in STD_LOGIC;
o_DOUT : buffer UNSIGNED(15 downto 0)
);
end sum_register;
architecture arch_1 of sum_register is
begin
process(i_CLEAR,i_LOAD,i_SHIFT, i_DIN)
begin
IF (i_CLEAR = '1') THEN
o_DOUT <= "0000000000000000";
ELSIF (i_LOAD = '1') THEN
o_DOUT(15 downto 7) <= i_DIN;
ELSIF (i_SHIFT = '1') THEN
o_DOUT <= o_DOUT SRL 1;
END IF;
end process;
end arch_1;
You need to use a clock signal in the circuit to make this synchronous, you will need an input in your entity like this:
i_CLOCK : in STD_ULOGIC;
After this you will need to make your process sensitivy to the clock:
process(i_CLOCK)
And your architecture will change to this:
architecture arch_1 of sum_register is
SIGNAL r_DOUT : unsigned(15 downto 0);
begin
process(i_CLOCK)
begin
IF rising_edge(i_CLOCK) THEN
IF (i_CLEAR = '1') THEN
r_DOUT <= "0000000000000000";
ELSIF (i_LOAD = '1') THEN
r_DOUT(15 downto 8) <= i_DIN;
ELSIF (i_SHIFT = '1') THEN
r_DOUT <= r_DOUT SRL 1;
END IF;
END IF;
end process;
o_DOUT <= r_DOUT;
end arch_1;
With this architecture you will need a unsigned signal to make atribution for your output o_DOUT, with this you can change your o_DOUT output to output type again (not buffer).
NOTE: The clock signal needs to be the same for all blocks!
I am doing a project in college and want to produce a triangular wave using a DAC2904 and a Spartan 3 xc3s5000 board.
I have written code for it but is not working.
I don't know may be it is the problem in code or in my ucf file:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity traingular is
Port (
clk : in std_logic; -- on board clock
reset : in std_logic;
dac_clk : out std_logic; -- clk for dac module
output : out std_logic_vector(13 downto 0); -- output to dac
wr_dac : out std_logic -- pulse given to write pin of dac ic.
);
end traingular;
architecture Behavioral of traingular is
signal counter : unsigned(3 downto 0);
signal divide : std_logic_vector(15 downto 0);
signal sampling_clk , clk_s : std_logic;
signal decade : std_logic_vector(3 downto 0);
-- decade counter used because on board clk freq is 40 hz
-- so the code written below reduce the freq which is applied to dac module very much
begin
process(clk, reset)
begin
if (reset = '1' ) then
decade <= (others => '0');
elsif (clk' event and clk = '1') then
if (decade = "1010") then
decade <= (others => '0');
else
decade <= std_logic_vector(unsigned(decade) + 1);
end if;
end if;
end process;
clk_s <= '1' when decade = "1010" else
'0';
process(clk_s , reset)
begin
if (reset='1') then
divide <= (others => '0');
elsif (clk_s'event and clk_s = '1') then
divide <= std_logic_vector(unsigned(divide) + 1);
end if;
end process;
sampling_clk <= divide(2);
-- input click is still fast so clock is divided further
dac_clk <= sampling_clk;
wr_dac <= sampling_clk;
process(clk , reset)
begin
-- code below is for counter which will further feed to dac to produce traingular wave.
if (reset = '1' ) then
counter <= (others => '0');
elsif (clk' event and clk = '1') then
if (counter = "1010") then
counter <= (others => '0');
else
counter <= counter + 1;
end if;
end if;
end process;
output <= "0000000000" & std_logic_vector(counter); -- output to dac.
end Behavioral;
So, can you guys tell me what is the problem in my code.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_signed.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tri_wave is
Port ( clk : in STD_LOGIC;
rst :in STD_LOGIC;
up_step_size,down_step_size:in std_logic_vector(2 downto 0);
dac_out : out STD_LOGIC_VECTOR (7 downto 0));
end tri_wave;
architecture Behavioral of tri_wave is
signal dac_wav:std_logic_vector(7 downto 0);
signal count:std_logic_vector(7 downto 0);
signal dir:std_logic:='0';
begin
process(clk,rst,dir)
begin
if rst='1' then
count<=(others=>'0');
elsif dir='0' then
if clk'event and clk='1' then
if count="01111111" then
dir<='1' ;
else
count<= count + up_step_size;
end if;
end if;
elsif dir='1' then
if clk'event and clk='1' then
if count="10000000" then
dir<='0' ;
else
count<= count - down_step_size;
end if;
end if;
end if;
end process;
--dac_out<=count;
dac_out<=count(count'high) & count(6 downto 0);
end Behavioral;
i think this code gives u better idea just creaet tb and simulae i odelsim u will get it.