Adding two bit_vector in VHDL return error "(vcom-1581) No feasible entries for infix operator '+'." - vhdl

Question

This is my code for converting binary to BCD in VHDL
library ieee;
use ieee.numeric_bit.all;
entity bin2bcd is
port (bin : in bit_vector(3 downto 0) := "0000";
clk : in bit;
bcdout : out bit_vector(4 downto 0) := "00000");
end bin2bcd;
architecture bin2bcdarch of bin2bcd is
begin
process(clk)
variable gt9 : bit;
variable temp : bit_vector(3 downto 0) := "0110";
variable bcdout_temp : bit_vector(4 downto 0);
begin
if clk'event and clk = '1' then
gt9 := bin(3) and(bin(2) or bin(1));
if gt9 = '1' then
bcdout_temp := ('0' & bin) + ('0' & temp);
else
bcdout_temp := ('0' & bin);
end if;
end if;
bcdout <= bcdout_temp;
end process;
end bin2bcdarch;
The problem is when i am trying to add the two bit_vector in the line
bcdout_temp := ('0' & bin) + ('0' & temp);
using "+" operator, that I get the error
(vcom-1581) No feasible entries for infix operator '+'.
Now, I looked in the web and most of the solutions are for when I use std_logic_vector.
The code works fine if I use std_logic_vector but not when I use bit_vector.
Is there any solution to the problem as to why I am getting the error?

Answer 1

You can add bit vectors if you use ieee.numeric_bit_unsigned.all which is part of VHDL-2008. The numeric_std package you're using does not define addition for bit vector.

Answer 2

If you find your old CAD lab software doesn't support numeric_bit_unsigned you can use type conversions, numeric_bit contains declarations for types signed and unsigned:
library ieee;
use ieee.numeric_bit.all;
entity bin2bcd is
port (bin : in bit_vector(3 downto 0) := "0000";
clk : in bit;
bcdout : out bit_vector(4 downto 0) := "00000");
end bin2bcd;
architecture bin2bcdarch of bin2bcd is
begin
process(clk)
variable gt9 : bit;
variable temp : unsigned(3 downto 0) := "0110"; -- was bit_vector
variable bcdout_temp : unsigned(4 downto 0); -- was bit vector
begin
if clk'event and clk = '1' then
gt9 := bin(3) and(bin(2) or bin(1));
if gt9 = '1' then
bcdout_temp := '0' & unsigned(bin) + ('0' & temp); -- type conversion
else
bcdout_temp := '0' & unsigned(bin); -- type conversion
end if;
end if;
bcdout <= bit_vector(bcdout_temp); -- type conversion
end process;
end bin2bcdarch;
Note temp can also be class constant instead of variable, it's not assigned other than an initial value.
From your comments using WARP2 to synthesis (presumably CPLDs) I recall that it was originally developed to use AHDL as input description and that support for VHDL and Verilog were an afterthought.
You're likely seeing limitations based on what VHDL constructs map to AHDL constructs that are supported for synthesis.
The way to deal with such limitations may be to describe troublesome parts of designs as a dataflow description:
entity bin2bcd is
port (
bin: in bit_vector(3 downto 0);
clk: in bit;
bcdout: out bit_vector(4 downto 0)
);
end entity bin2bcd;
architecture dataflow of bin2bcd is
signal bcdout_temp: bit_vector(4 downto 0);
begin
bcdout_temp(4) <= bin(3) and ( bin(2) or bin(1) ); -- gt9
bcdout_temp(3) <= not bcdout_temp(4) and bin(3); -- zero if gt9
bcdout_temp(2) <= ( bin(3) and bin(2) and bin(1)) or
(not bin(3) and bin(2));
bcdout_temp(1) <= ( bcdout_temp(4) and not bin(1)) or -- gt9 XOR bin(1)
(not bcdout_temp(4) and bin(1));
bcdout_temp(0) <= bin(0); -- doesn't change
REG5:
process (clk)
begin
if clk'event and clk = '1' then
bcdout <= bcdout_temp;
end if;
end process;
end architecture;
While there's no guarantee of this would work better (although likely) it also simulates as VHDL with a testbench:
library ieee;
use ieee.numeric_bit.all;
entity bin2bcd_tb is
end entity;
architecture foo of bin2bcd_tb is
signal bin: bit_vector(3 downto 0);
signal clk: bit;
signal bcdout: bit_vector(4 downto 0);
begin
DUT:
entity work. bin2bcd (dataflow)
port map (
bin => bin,
clk => clk,
bcdout => bcdout
);
CLOCK:
process
begin
wait for 5 ns;
clk <= not clk;
if now > 160 ns then
wait;
end if;
end process;
STIMULI:
process
begin
for i in 0 to 2 ** bin'length - 1 loop
bin <= bit_vector(to_unsigned(i, bin'length));
wait for 10 ns;
end loop;
wait;
end process;
end architecture;
And shows it gives the right results:
bin is displayed in decimal while bcdout is displayed in hex.