I am new to HDL and just wanted to confirm whether these lines of code are written in VHDL or Verilog?
DE0_SOPC DE0_SOPC_inst(
// 1) global signals:
.clk(CLOCK_50),
.pll_cpu(),
.pll_sdram(DRAM_CLK),
.reset_n(system_reset_n));
It's Verilog. It is an instantiation of a module inside another. This is how you do it in Verilog; it is not how you do it in VHDL.
Yes. These are verilog code lines. As per your previous comments, Type: .v files belong to verilog codes.
Related
I have an example project in Verilog originally was for ICE40 FPGA, I want to import it to Xilinx FPGA for resource reason. There is this SB_IO primitive in ICE40 that defines input/output ports. I don't quite understand it and wondering if there is similar or equivalent primitive in Xilinx FPGA? Or how to translate it into Xilinx FPGA domain?
The example code is as follows:
SB_IO #(
.PIN_TYPE(6'b010100),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0),
.IO_STANDARD("SB_LVCMOS")
) iob_data_I[SDW-1:0] (
.PACKAGE_PIN(disp_data),
.CLOCK_ENABLE(1'b1),
.OUTPUT_CLK(clk),
.D_OUT_0(phy_data)
);
Please help, thanks!
This looks like the SB_IO is being used as an output register. So the Xilinx equivalent would be FDRE or another DFF primitive with the (*IOB="TRUE"*) attribute set on it to encourage it to be packed into the IO register block.
Is it possible to use VHDL-2008 hierarchical references / external names to reference Verilog nets? Questa Sim (10.6c) stops the simulation with this error message:
vsim-8509: The object class "SIGNAL" of "dut_i.my_net" is different from the class "net" of the denoted object.
Here's the VHDL code that fails:
alias my_alias is << signal dut_i.my_net : std_logic >>;
According to the Questa User Manual:
Questa SIM supports the IEEE 1076-2008 standard “external name” syntax
that allows you to make hierarchical references from VHDL to VHDL.
Currently, these references can cross Verilog boundaries, but they
must begin and end in VHDL.
Thus, the answer is no.
Questa does provide a set of Signal Spy procedures to access your Verilog signals via string names. You must also turn on optimization visability to access these signals since the strings are not parsed until run-time.
Our simulator allows VHDL / Verilog mixed and our design uses an IP that written in VHDL (otherwise, our design is mostly in Systemverilog).
We are having problems as parameter overriding is not correctly working and we found the following statements from Simulator's documentation:
"By default, when a Verilog module is instantiated inside a VHDL design unit and default binding is done, VHDL generics are mapped to Verilog parameters using positional mapping."
It is saying that mappings of VHDL generics to Verilog parameters are done using positional mapping, not named mapping. The simulator offers a special option to change the binding rule to "named mapping" and that solved our problem.
My question is which standard specifies the binding rule when it comes to Verilog inside VHDL (or VHDL inside Verilog)?
Or, is this an arbitrary choice the simulator vendor made?
The unfortunate truth is there is no standard for interoperability between standards. Why this is the case may be highly opinionated. But I can say that if more people bring this issue up to their vendors, the more likely it may get addressed.
I can't find an example in doc to convert a VHDL code to Verilog with icarus. I found how to do verilog to VHDL here.
I tried to modify the command to do VHDL convertion on this code :
$ iverilog -tvlog95 -o button_deb.v button_deb.vhdl
button_deb.vhdl:3: syntax error
I give up.
But I've got a syntax error. Is my VHDL code is wrong ? Or is it iverilog command that is wrong ?
There's no Verilog target, so you can't generate Verilog output, and VHDL compilation is still experimental anyway. You could ask on the mailing list to make sure there's nothing under the hood which could help. VHDL to Verilog conversion is only possible in relatively simple cases (synthesisable code should be Ok), so you may have to do it manually anyway.
It seems that some support has arrived in the meantime (mainly using -g2005-sv, -g2009, or -g2012 switch) . Try this:
iverilog -g2012 -tvlog95 -o button_deb.v button_deb.vhd
If you pay closer attention to the output you'll see that in this way you'll loose the two generic at the entity interface. Using vhdlpp directly could be useful:
/path/to/vhdlpp button_deb.vhd > button_deb.v
I was wondering if its possible to generate vhdl code from a schematic in xilinx. I know that the reverse is feasible. I want this to be done cause i am curious how the code will be like after i have completed the datapath of a mips R2000 and also its an easy way to modify large schematics by changing key lines in the code. I have used both schematics and vhdl but i d like to see the whole datapath written in a vhdl. I use Xilinx 12.3. Thanks!
The option is in the design menu -> select a .sch file in the implementation window and then click the "View HDL functional model". This will generate the vhdl code for the selected schematic. :o
you can convert your schematic design into the HDL model. below the implementation under design, utilities tap to click on view HDL functional model which create the HDL file from the schematic which is .vhf for VHDL and .vf for the Verilog change this file into the .vhd for the VHDL and .v for the Verilog after then you can easily add this design into your vivado projects
If you are using Vivado 2018.2, you can use write_vhdl in the Tcl console followed by the file's name to which you want to write the VHDL.
For example,
write_vhdl Drive_Letter:\File_Location\Schematic_to_vhdl.vhd