I can't find an example in doc to convert a VHDL code to Verilog with icarus. I found how to do verilog to VHDL here.
I tried to modify the command to do VHDL convertion on this code :
$ iverilog -tvlog95 -o button_deb.v button_deb.vhdl
button_deb.vhdl:3: syntax error
I give up.
But I've got a syntax error. Is my VHDL code is wrong ? Or is it iverilog command that is wrong ?
There's no Verilog target, so you can't generate Verilog output, and VHDL compilation is still experimental anyway. You could ask on the mailing list to make sure there's nothing under the hood which could help. VHDL to Verilog conversion is only possible in relatively simple cases (synthesisable code should be Ok), so you may have to do it manually anyway.
It seems that some support has arrived in the meantime (mainly using -g2005-sv, -g2009, or -g2012 switch) . Try this:
iverilog -g2012 -tvlog95 -o button_deb.v button_deb.vhd
If you pay closer attention to the output you'll see that in this way you'll loose the two generic at the entity interface. Using vhdlpp directly could be useful:
/path/to/vhdlpp button_deb.vhd > button_deb.v
Related
In my VHDL design there is a 16-bits std_logic_vector. The bit in position 15 is currently not used and the synthesizer (SynplifyPro) throws a warning saying that bit is not used and will be pruned:
#W:CL190 : DATAGEN.vhd(93) | Optimizing register bit MYREG(15) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
#W:CL260 : DATAGEN.vhd(93) | Pruning register bit 15 of MYREG(15 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
As suggested by the synthesizer, I have added the required attribute and I was able to get rid of these warnings. To add these attributes, I had to include the Synplify library:
library synplify;
at the top of the file, and then define the attribute as follows:
ATTRIBUTE SYN_PRESERVE : BOOLEAN;
ATTRIBUTE SYN_PRESERVE OF MYREG : SIGNAL IS TRUE;
If I try to run ModelSim on Post-Synthesis everything is fine. However, when I try to run ModelSim on Pre-synthesis, it gives me the error:
** Error: .../DATAGEN.vhd(20): (vcom-1598) Library "synplify" not found.
I believe that the problem is because Pre-Synthesis simulation is not supposed to use this library. In fact, if I remove this everything works. The reason for which I would like to keep using the Pre-Synthesis simulation is because it is much faster than Post-Synthesis. However, this issue forces me to keep commenting out this lib for Pre-synthesis and putting it back for Post-synthesis?
Is it possible to use something like conditional include?
Note: I prefer to keep the unused bits, therefore adding the attribute for avoid pruning works fine for me.
Is it possible to use something like conditional include?
The upcoming VHDL-2019 standard supports conditional compilation and some simulators, for example RivieraPro, have started to support that. With such support you can do things like
`if INCLUDE_SYNPLIFY = "true" then
library synplify;
`end if
I don't think ModelSim has that yet but what you can do is to just define a synplify library with vlib and include that when calling vsim. If you are using VUnit you can simply add the following to your run script
prj.add_library("synplify")
I am trying to formally verify a small module in a very big Project code. I have anayzed and elaborated the design. I cannot verify the small module because the tool gives me a "Found Combinational Loop" error.
I am quite sure that this small module is not affected by this Loop error. So i want to avaid getting this error. Is it even possible?
Thanks!
Not sure what tool you used, in JasperGold formal tool, you can use following command setting to break a combinational loop.
stopat u_DUT.signal_a
Just put it before prove -all in your tcl file (if you uses a tcl file to run your tool).
Have a look at stopat command in JapserGold manual for further information in your cases to see if you can easily break the comb loop.
I have generated dump output files using command -fdump-tree-all and -fdump-rtl-all and I got a lot of dump files. I have read that the codes in GIMPLE are in pseudo-C syntax and RTL dump files are too low level to be understood. Is there any ways to understand GIMPLE and RTL dump files? Any software that can convert it to C code or something useful? Any tutorial to learn to understand it? Thanks
the best way to do it (for me) is to dump some examples and understand by yourself the emitted code. It's not difficult, there are some change from the original code (like cycles are transformed in if with goto), there are a lot of passes in gcc and my advice is to dump what you need. In my case i use frequently the commands:
-fdump-tree-lower
-fdump-tree-cfg
-fdump-tree-ssa
-fdump-tree-optimized (it's the last pass before going into rtl passes)
rtl is almost incompressible and it's needed a great understanding over that dialect
I was wondering if its possible to generate vhdl code from a schematic in xilinx. I know that the reverse is feasible. I want this to be done cause i am curious how the code will be like after i have completed the datapath of a mips R2000 and also its an easy way to modify large schematics by changing key lines in the code. I have used both schematics and vhdl but i d like to see the whole datapath written in a vhdl. I use Xilinx 12.3. Thanks!
The option is in the design menu -> select a .sch file in the implementation window and then click the "View HDL functional model". This will generate the vhdl code for the selected schematic. :o
you can convert your schematic design into the HDL model. below the implementation under design, utilities tap to click on view HDL functional model which create the HDL file from the schematic which is .vhf for VHDL and .vf for the Verilog change this file into the .vhd for the VHDL and .v for the Verilog after then you can easily add this design into your vivado projects
If you are using Vivado 2018.2, you can use write_vhdl in the Tcl console followed by the file's name to which you want to write the VHDL.
For example,
write_vhdl Drive_Letter:\File_Location\Schematic_to_vhdl.vhd
I am running some VHDL through ModelSim. Each error and warning has its own error code (like this: (vcom-1292) Slice range direction "downto" specified in slice with prefix of unknown direction. This is just an example message; I understand what it means.
I assume that Mentor has a list of all possible error codes and a more elaborate description of what they mean, and how to avoid them. I did not find this error code in the PDFs that come with ModelSim, nor did I find it through Google. Any pointers anybody?
There is a modelsim command called verror with an -all option to list them all, and other options to inspect the messages further.
if you are interested in finding out information about a certain error then use the verror command in the Questasim GUI.
verror
Better than going through the entire list. :)