I have an example project in Verilog originally was for ICE40 FPGA, I want to import it to Xilinx FPGA for resource reason. There is this SB_IO primitive in ICE40 that defines input/output ports. I don't quite understand it and wondering if there is similar or equivalent primitive in Xilinx FPGA? Or how to translate it into Xilinx FPGA domain?
The example code is as follows:
SB_IO #(
.PIN_TYPE(6'b010100),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0),
.IO_STANDARD("SB_LVCMOS")
) iob_data_I[SDW-1:0] (
.PACKAGE_PIN(disp_data),
.CLOCK_ENABLE(1'b1),
.OUTPUT_CLK(clk),
.D_OUT_0(phy_data)
);
Please help, thanks!
This looks like the SB_IO is being used as an output register. So the Xilinx equivalent would be FDRE or another DFF primitive with the (*IOB="TRUE"*) attribute set on it to encourage it to be packed into the IO register block.
Related
Is it possible to use VHDL-2008 hierarchical references / external names to reference Verilog nets? Questa Sim (10.6c) stops the simulation with this error message:
vsim-8509: The object class "SIGNAL" of "dut_i.my_net" is different from the class "net" of the denoted object.
Here's the VHDL code that fails:
alias my_alias is << signal dut_i.my_net : std_logic >>;
According to the Questa User Manual:
Questa SIM supports the IEEE 1076-2008 standard “external name” syntax
that allows you to make hierarchical references from VHDL to VHDL.
Currently, these references can cross Verilog boundaries, but they
must begin and end in VHDL.
Thus, the answer is no.
Questa does provide a set of Signal Spy procedures to access your Verilog signals via string names. You must also turn on optimization visability to access these signals since the strings are not parsed until run-time.
Our simulator allows VHDL / Verilog mixed and our design uses an IP that written in VHDL (otherwise, our design is mostly in Systemverilog).
We are having problems as parameter overriding is not correctly working and we found the following statements from Simulator's documentation:
"By default, when a Verilog module is instantiated inside a VHDL design unit and default binding is done, VHDL generics are mapped to Verilog parameters using positional mapping."
It is saying that mappings of VHDL generics to Verilog parameters are done using positional mapping, not named mapping. The simulator offers a special option to change the binding rule to "named mapping" and that solved our problem.
My question is which standard specifies the binding rule when it comes to Verilog inside VHDL (or VHDL inside Verilog)?
Or, is this an arbitrary choice the simulator vendor made?
The unfortunate truth is there is no standard for interoperability between standards. Why this is the case may be highly opinionated. But I can say that if more people bring this issue up to their vendors, the more likely it may get addressed.
I am new to HDL and just wanted to confirm whether these lines of code are written in VHDL or Verilog?
DE0_SOPC DE0_SOPC_inst(
// 1) global signals:
.clk(CLOCK_50),
.pll_cpu(),
.pll_sdram(DRAM_CLK),
.reset_n(system_reset_n));
It's Verilog. It is an instantiation of a module inside another. This is how you do it in Verilog; it is not how you do it in VHDL.
Yes. These are verilog code lines. As per your previous comments, Type: .v files belong to verilog codes.
I'm having some trouble designing a single port rom onto a spartan 6 board. I use the provided core generator to create block memory and choose single port rom with 32 bit width and 256 depth with a coe file that just counts from 0 to 255. I drop the rom into my vhdl as a component and add the XilinxCoreLib as a library. When I try to generate the programming file I get the translate error:
logical block 'rom1' with type 'rom' could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
case mismatch between the block name and the edif or ngc file name, or the
misspelling of a type name. Symbol 'rom' is not supported in target
'spartan6'.
I'm currently using Xilinx ISE 13.1 if that helps. I feel like this should be really easy to do but I haven't been able to find how to do it.
Edit: Thanks everyone, was a combination of things. Wrong speed grade, and didn't add a copy of the ngc file to my working directory. I'll use arrays in the future.
Easiest way is to forget the vendor tools altogether and simply declare a constant array!
If this is in a package separate from the rest of the design, a few lines of printf's or a simple script can generate the VHDL boilerplate around the contents, which come from your assembler or whatever tool creates the actual data
Since you're adding a Xilinx generated core to your design in ISE, you need to add both the VHD file and the NGC file via "Add Source" via the Project menu.
Even easier, depending on how large your ROM needs to be and what data goes into it, would be to not even bother with a Xilinx core, but to use pure VHDL to declare a constant array and initialization values right in your VHDL file. Here is an example:
type array_ROM is array (0 to NUMBER_OF_ROWS-1) of std_logic_vector (ROM_BITWIDTH-1 downto 0);
signal my_ROM : array_ROM
:=
(
x"12345678",
x"ABCDEF01",
...
x"01010101"
);
Now, you don't put the elipsis (...) in that initialization list, just put rows of constants with bit widths matching ROM_BITWIDTH. The NUMBER_OF_ROWS is the number of address locations you need in the ROM. In this example, ROM_BITWIDTH would have to be set to 32 as I've used 32-bit hexadecimal constants in the initialization list. Being a signal, it's actually modifiable, so if you need it to be constant, just use "constant" instead of signal.
I guess the problem is, as the message says, a misspelling. to get the correct component declaration/instantiation, select your rom.xco in the design-window of ISE. then select "view vhdl instantiation template" from process window. use the component declaration and instantiation described therein.
There are a number of things that can cause this problem, one is that you are using a blocck that was generated for another FPGA family and using it inside the Spartan6. the other is that you may have generated the ROM using an older version of the tool and the wrapper for the ROM has changed since then.
You can either generate a anrray like Brian suggested and forgetting about the tool specific ROM type, or re-generate the IP under your curernt project settings and see how it goes.
I was wondering if its possible to generate vhdl code from a schematic in xilinx. I know that the reverse is feasible. I want this to be done cause i am curious how the code will be like after i have completed the datapath of a mips R2000 and also its an easy way to modify large schematics by changing key lines in the code. I have used both schematics and vhdl but i d like to see the whole datapath written in a vhdl. I use Xilinx 12.3. Thanks!
The option is in the design menu -> select a .sch file in the implementation window and then click the "View HDL functional model". This will generate the vhdl code for the selected schematic. :o
you can convert your schematic design into the HDL model. below the implementation under design, utilities tap to click on view HDL functional model which create the HDL file from the schematic which is .vhf for VHDL and .vf for the Verilog change this file into the .vhd for the VHDL and .v for the Verilog after then you can easily add this design into your vivado projects
If you are using Vivado 2018.2, you can use write_vhdl in the Tcl console followed by the file's name to which you want to write the VHDL.
For example,
write_vhdl Drive_Letter:\File_Location\Schematic_to_vhdl.vhd