RAM to read/write in VHDL - vhdl

Question

I'm trying to use RAM in order to read/write. My address is an integer value and it should be a memory of integers. This is my code below but i keep getting an error.
This is from my data path where the address selection is from a register of integers.
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Mem is
generic( width: integer:=4;
depth: integer:=4;
addr: integer:=2);
port( Clock: in std_logic;
Enable: in std_logic;
Read: in std_logic;
Write: in std_logic;
Read_Addr: in integer;
Write_Addr: in integer;
Data_in: in integer;
Data_out: out integer
);
end Mem;
--------------------------------------------------------------
architecture behav of Mem is
type ram_type is array (0 to 31) of
integer;
signal tmp_ram: ram_type;
begin
-- Read Functional Section
process(Clock, Read)
begin
if (Clock'event and Clock='1') then
if Enable='1' then
if Read='1' then
-- buildin function conv_integer change the type
-- from std_logic_vector to integer
Data_out <= tmp_ram(conv_integer(Read_Addr));
else
Data_out <= (Data_out'range => 'Z');
end if;
end if;
end if;
end process;
-- Write Functional Section
process(Clock, Write)
begin
if (Clock'event and Clock='1') then
if Enable='1' then
if Write='1' then
tmp_ram(conv_integer(Write_Addr)) <= Data_in;
end if;
end if;
end if;
end process;
end behav;
----------------------------------------------------------------
Error:
Error (10514): VHDL aggregate error at Mem.vhd(41): can't determine type of aggregate -- found 0 possible types

Answer 1

Your faulty code is:
if Read='1' then
-- buildin function conv_integer change the type
-- from std_logic_vector to integer
Data_out <= tmp_ram(conv_integer(Read_Addr));
else
Data_out <= (Data_out'range => 'Z'); -- Faulty line
end if;
Data_out is an integer, not a std_logic_vector or derived type. Thus, it doesn't have a range (only arrays do, std_logic_vector beeing defined as an array of std_logic). Furthermore, it can't take the value of 'Z' since it is not an std_logic; integers can only be assigned integer values.
If you need Data_out to become high-impedance when enable is '1' and read is '0' as you described, you will need your memory output to use std_logic_vector or signed/unsigned.
Also, I should advise you against using integers without range if your target is synthesis. By VHDL standard, integers are 32 bits. Synthesis tool may optimized the netlist and use less bits, but you shouldn't count on it. Either constrain the range of your integers (signal x: integer range -4 to 3) or use signed/unsigned.