I am using code from this website code:
entity triangular is
port (clk : in std_logic;
wave_out : out std_logic_vector(7 downto 0);
reset :in std_logic
);
end triangular;
architecture Behavioral of triangular is
signal count,count2 : integer := 0;
signal direction : std_logic := '0';
begin
process(clk,reset)
begin
if(reset = '1') then
count <= 0;
count2 <= 129;
elsif(rising_edge(clk)) then
--"direction" signal determines the direction of counting - up or down
if(count = 253) then
count <= 0;
if(direction = '0') then
direction <= '1';
count2 <= 126;
else
direction <= '0';
count2 <= 129;
end if;
else
count <= count + 1;
end if;
if(direction = '0') then
if(count2 = 255) then
count2 <= 0;
else
count2 <= count2 + 1; --up counts from 129 to 255 and then 0 to 127
end if;
else
if(count2 = 255) then
count2 <= 0;
else
count2 <= count2 - 1; --down counts from 126 to 0 and then 255 to 128
end if;
end if;
end if;
end process;
wave_out <= conv_std_logic_vector(count2,8);
end Behavioral;
and I am getting output in digital format but I want to get output as given in the website link. How can I do that? I am new to VHDL working this as assignment.
(click to enlarge)
In Xilinx ISE simulator simulation result only in digital value instead of ISim you can use ModelSim simulator
In that ModelSim simulator Analog Data option Available
In Vivado Simulator Also have analog data view option
Related
I am trying to interface the output of my FPGA onto a DAC. I am using the PmodDA2 DAC. The trouble I am having is working out how to output the data from a 16bit register into 1 bit per clock cycle.
I have studied the timing diagram and understand that CS needs to send a pulse before data transmission begins.
I have tried using the necessary resets and other features as applicable within my design as a whole.
I tried implementing a count to cycle between 0 to 16/17 and when it was at the beginning it would set CS to high and begin transmission. However I did not believe this would be at all the correct way to do it.
architecture Behavioral of DAC is
signal count : integer range 0 to 15;
signal selected : std_logic;
signal data_storage : std_logic_vector(15 downto 0);
begin
process(D_DAC, CE_DAC, RES_DAC, RES_DAC, data_storage)
begin
if RES_DAC = '1' then
data_storage <= "0000000000000000";
end if;
if rising_edge(CLK_DAC) then
if CE_DAC = '1' then
data_storage <= D_DAC;
end if;
end if;
end if;
end process ;
CS_DAC <= CE_DAC;
SCLK_DAC <= CLK_DAC;
DATA1_DAC <= data_storage;
end Behavioral;
I'm getting myself very confused over this.
I'd appreciate any help.
************************EDIT************************
I have had another go at implementing the counter...
process(D_DAC, CE_DAC, CLK_DAC, RES_DAC, data_storage)
begin
if RES_DAC = '1' then
data_storage <= "0000000000000000";
cound <= 0;
selected <= '0';
elsif rising_edge(CLK_DAC) then
if CE_DAC = '1' then
if count = 0 then
selected <= '1';
end if;
if selected = 1 then
if count = 15 then
count <= 0;
selected <= '0';
else
count <= count + 1;
data_storage <= D_DAC;
end if;
end if;
end if;
end if;
end process ;
CS_DAC <= CE_DAC;
SCLK_DAC <= CLK_DAC;
DATA1_DAC <= data_storage;
end Behavioral;
I want to make a UART receiver that reads 8 consecutives bits with a parity bit at the end and with a simple stop bit. My FPGA have a clock of 100Mhz and the data that are transmitted to the uart have a rate of 56700 bauds. The dividing factor is 1736 (56700 * 1736 ≈ 100Mhz). The two outputs are the message of the input decoded by the uart and an error signal that indicates if the uart have correctly read the input. This is what I have :
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity uart_receiver is
generic (
clksPerBit : integer := 1736 -- Needs to be set correctly
);
port (
clk : in std_logic;
clk_en_uart : in std_logic ;
reset : in std_logic;
uart_rx : in std_logic;
error : out std_logic;
char : out std_logic_vector(7 downto 0)
);
end uart_receiver;
architecture uart_receiver_arch of uart_receiver is
type etat is (init, start_bit, receiving_bits, parity_bit,
stop_bit );
signal current_state : etat := init ;
signal error_signal : std_logic := '0';
signal clk_count : integer range 0 to clksPerBit-1 := 0;
signal bit_index : integer range 0 to 7 := 0; -- 8 Bits Total
signal data_byte : std_logic_vector(7 downto 0) := (others => '0');
begin
process (clk_en_uart)
begin
if rising_edge(clk_en_uart) then
end if;
end process;
process (clk,reset)
variable check_parity : integer range 0 to 7 := 0;
begin
if (reset = '1') then
current_state <= init;
error_signal <= '0';
clk_count <= 0;
bit_index <= 0;
data_byte <= (others => '0');
elsif rising_edge(clk) then
case current_state is
when init =>
clk_count <= 0;
Bit_Index <= 0;
if uart_rx = '0' then -- Start bit detected
current_state <= start_bit;
else
current_state <= init;
end if;
when start_bit =>
if clk_count = (clksPerBit-1)/2 then
if uart_rx = '0' then
clk_count <= 0; -- reset counter since we found the middle
current_state <= receiving_bits;
else
current_state <= init;
end if;
else
clk_count <= clk_count + 1;
current_state <= start_bit;
end if;
when receiving_bits =>
if clk_count < clksPerBit-1 then
clk_count <= clk_count + 1;
current_state <= receiving_bits;
else
clk_count <= 0;
data_byte(bit_index) <= uart_rx;
if bit_index < 7 then
bit_index <= bit_index + 1;
current_state <= receiving_bits ;
else
bit_index <= 0;
current_state <= parity_bit;
end if;
end if;
when parity_bit =>
if clk_count < clksPerBit-1 then
clk_count <= clk_count + 1;
current_state <= parity_bit;
else
for k in 0 to 7 loop
if ( data_byte(k) = '1' ) then
check_parity := check_parity + 1 ;
end if;
end loop;
if((uart_rx = '1' and check_parity mod 2 = 0) or (uart_rx = '0' and check_parity mod 2 = 1)) then
error_signal <= '1' ;
else
error_signal <= '0';
end if ;
current_state <= stop_bit;
end if;
when stop_bit =>
if clk_count < clksPerBit-1 then
clk_count <= clk_count + 1;
current_state <= stop_bit ;
else
clk_count <= 0;
current_state <= init;
end if;
when others =>
current_state <= init;
end case;
end if;
char <= data_byte ;
error <= error_signal ;
end process;
end uart_receiver_arch;
So there's a phase shift between the data that is transmitted to the uart and his clock. If there's a phase shift, I'm not reading the data at the right time. I think that this code is sufficient to solve this problem. But, I've created a clock_divider and I can't seem to find a way to use it in this code. This is my clock divider :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clock_divider is
generic (divfactor : positive := 1736);
Port (clk,clk2, reset : in STD_LOGIC ;
clkdiv, activationsig : out STD_LOGIC );
end clock_divider;
architecture clock_divider_arch of clock_divider is
begin
process(clk,reset)
variable clksigv : std_logic := '0' ;
variable activationsigv : std_logic := '0' ;
variable count : integer := 0 ;
begin
if (reset = '1') then
clksigv := '0' ;
activationsigv := '0' ;
count := 0 ;
elsif ( rising_edge(clk) ) then
count := count + 2 ;
if (activationsigv = '1') then
activationsigv := '0';
end if;
if ( count >= divfactor - 1 ) then
clksigv := not(clksigv) ;
if ( clksigv = '1' ) then
activationsigv := '1' ;
end if;
count := 0 ;
end if ;
end if ;
clkdiv <= clksigv ;
activationsig <= activationsigv;
end process ;
end clock_divider_arch;
The outputs of this clock divider are the clock divided and the activation signal that, when it is at '1', I have to read the data in the uart. So, the two outputs should also be inputs of the uart. In the uart_recevier, clk_en_uart is actually the clock divided, but I'm not using it because I don't know how.
I think that the solution is to 'activate' this divided clock when I enter in the start_bit case so that I have two clocks with the same phase and the same frequency, but I also think that it impossible to set a phase for a clock.
I'm not sure that I've clearly adressed my problem. If there's something that you don't understand in my code or in my explanation, feel free to ask questions.
Thank you for your help, hoping that I find a solution.
Sounds like the suggested solution is complicated for this problem.
A usual approach is that the receiver justs look for the falling edge of the start bit, then count for half a bit time (1736 / 2 cycles in your case), then samples the start bit value there, and subsequently samples the data, parity and stop bit values after each full bit time (1736 cycles in your case). After that start over looking for a new falling edge of the start bit.
The difference between the transmitter and receiver frequencies are then (usually) so small that the sample time will be practically in the middle for messages of only 11 bits at relative low bitrate, and the counter restart at falling edge of start bit ensures that any effect of long time frequency difference is removed.
i'm working on a project using vhdl to configure a fpga board spartan 3E. what i have to do is a genius puzzle, in my main code there is a state machine to control the logic.
everything works well when i simulate the code using xilinx simulator but when i run the .bit file to the FPGA board what happens is that the first led of the sequence turns on and then turns off, this should happen but then when i click the right button it just stop working and the next sequence is never shown.
of course there is a issue of deboucing the buttons, and that's the reason i'm using a counter to prevent the repic to bug the system.
i'm working hard on this code to function but this issue doesn't go away, maybe i'm doing something wrong i don't know or i'm not doing something i should.
here is my main code, which is the state machine and a clock proccess with the counter.
Flag_conte = starts ou blocks the counter
Flag_estou_contando = 1=counting, 0= not counting, 3= just finished count.
BCD = board buttons IN
LEDs = corresponds to 4 leds that will show the sequence in the game
entity Algoritmo is
port(
clk: in std_logic;
BCD: in std_logic_vector (3 downto 0);
botaoStart: in std_logic;
botaoReset: in std_logic;
seven_seg: out std_logic_vector(6 downto 0);
anode: out std_logic_vector(3 downto 0);
LEDS: out std_logic_vector(3 downto 0)
);
END Algoritmo;
architecture Behavioral of Algoritmo is
subtype state_type is integer range 5 downto 0;
signal state, nextstate: state_type:=0;
signal Inicio, nclk: std_logic:= '0';
--variable posicaoAtual: integer :=0;
type mem1 is array (0 to 13) of std_logic_vector (3 downto 0);
constant vetorSequencia: mem1 := ( "0001", "0010", "0100", "1000", "0001", "0010", "0100", "1000", "0001", "0010", "0100", "1000", "0001", "0010");
constant generic1hz: integer:= 12_500_000;
signal t3count:integer:=0;
signal posA, posB, signalScore, Flag_conte,
Flag_estou_contando:integer:=0;
signal valor: integer :=12_500_000;
Begin
-------------
process (state,BCD,botaoStart,Flag_estou_contando)
variable Pos: integer :=0;
variable score: integer:=0;
variable posicaoAtual: integer:=0;
variable tentativa: std_logic_vector (3 downto 0);
begin
case state is
when 0 => if (botaoStart = '0')
then nextstate <= 0;-- estado idle, esperando entrada do tclado,led1=1;
else nextstate <= 1;
end if;
when 1 =>-- if(Flag_estou_contando =0)then
if(nextstate=2)then
Flag_conte <=0;
nextstate <= 2;
else if (nextstate/=2)then
if (posicaoAtual < score)then
if(Flag_estou_contando=0)then
LEDS <= vetorSequencia(posicaoAtual);
posA <= posicaoAtual;
Flag_conte<=1;
valor<=10_000_000;
else if(Flag_estou_contando=1)then
LEDS <=vetorSequencia(posicaoAtual);
else if (Flag_estou_contando=3)then
--posicaoAtual:=0;
posicaoAtual := posicaoAtual + 1;
posA <= posicaoAtual;
nextstate <=1;
Flag_conte<=0;
end if;end if;end if;
else if(posicaoAtual = score)then
if(Flag_estou_contando=0)then
Flag_conte<=1;
valor<=10_000_000;
-- posicaoAtual :=0;
posA <= posicaoAtual;
else if(Flag_estou_contando=1)then
LEDS <=vetorSequencia(posicaoAtual);
nextstate<=1;
else if(Flag_estou_contando=3)then
posicaoAtual:=0;
posA <= posicaoAtual;
Flag_conte<=0;
nextstate <= 2;
end if;end if;end if;
end if;end if;
Flag_conte <=1;
end if;end if;
when 2 => --if(Flag_estou_contando=0)then
if (BCD = "0000")then
if(Flag_estou_contando=0)then
LEDS <= "0000"; --nextstate <= 2;
else if (Flag_estou_contando=1)then
nextstate<=2;
else if (Flag_estou_contando=3)then
Flag_conte <= 0;
nextstate<=3;
end if;end if;end if;
else if(BCD /= "0000")then
if(Flag_estou_contando=0)then
Flag_conte<=1;
valor<=200_000_000;
tentativa := BCD;
LEDS <= tentativa;
else if(Flag_estou_contando=3)then
nextstate <= 3;
else if(Flag_estou_contando=1)then
LEDS <= tentativa;
nextstate <=2;
end if;end if;end if;
end if;end if;
when 3 => if (vetorSequencia(Pos) = tentativa)then
if (Pos < score)then
nextstate <= 2;
Pos := Pos + 1;
posB <= Pos;
else if(Pos = score)then
score := score + 1;
signalScore <= score;
nextstate <= 1;
Pos := 0;
if (score = 15)-- if score =15 finish game
then nextstate <= 5;
end if;--end if
end if;end if;
else -- se estiver errado, perde o jogo
nextstate <= 4; -- goes to game over
end if;
when 4 => if (botaoReset = '1') -- game over
then nextstate <= 4;-- "U LOST nOOB"
elsif (botaoReset = '0')
then nextstate <= 0; --
end if;
when 5 => if (botaoReset = '1') -- jogo ganho
then nextstate <= 5; -- "GG"
elsif (botaoReset = '0')
then nextstate <= 0;
end if;
end case;
end process;
process (clk, Flag_conte)
variable sum, count :integer:=0;
begin
if rising_edge(clk) then
if(Flag_estou_contando = 0) then
if (Flag_conte = 1) then
count :=0;
Flag_estou_contando <=1;
end if;
end if;
if(Flag_estou_contando=3) then
if(Flag_conte =0)then
Flag_estou_contando <= 0;
else
Flag_estou_contando <=3;
end if;
end if;
if (Flag_estou_contando =1)then
if(count < valor)then
count := count + 1;
else
count:=0;
Flag_estou_contando <=3;
end if;
end if;
sum := sum +1;
if(sum = generic1hz)then -- 1hz generate
state <= nextstate;
nclk <= not nclk;
sum := 0;--restart count for 1hz generate
end if;
end if;
end process;
end Behavioral;
if i wasnt clear, please let me know i will try to explain better, if anyone could help i would be very greatful, thank you for your time.
You should try post place & route simulation to verify whats happen:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/pp_p_process_simulate_post_place.htm
With some family device you can use chipscope technology to debug:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx10/isehelp/ise_c_process_analyze_design_using_chipscope.htm
Sorry for my English.
Regards.
I have searched about this problem but it all seemed Greek to me so I came here as last effort.I have the following VHDL code that I want to be implemented on an fpga.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use work.conversions.all;
entity counter is
port ( clk_in: in std_logic; --new clock
target : in std_logic_vector(7 downto 1); --Set the target with the switches (SW7-SW1)
start : in std_logic; --Start/pause (SW0)
rst : in std_logic; --Reset (BT0)
LD : out std_logic_vector(7 downto 1); --Leds show the target at binary (LD7-LD1)
LD0 : out std_logic; --LD0 indicates thw the limit has been reached
seg : out std_logic_vector(7 downto 0); --7 segment display
digit : out std_logic_vector(3 downto 0)
);
end counter;
architecture Behavioral of counter is
begin
process(clk_in,target,rst)
variable timer : natural := 0;
variable counter : natural := 0;
variable display_counter : natural range 0 to 4 := 0;
begin
LD0 <= '0';
LD <= target; --Show the target at the leds
digit <= "1110"; --Last digit active
seg <= "00000011"; --Show zero
<--->if(rst='1') then --Reset counter
counter := 0;
timer := 0;
digit <= "1110"; --Last digit active
seg <= "00000011"; --Show zero
LD0 <= '0';
elsif rising_edge(clk_in) then
if(start = '0') then --Pause
--counter := counter;
elsif(counter = conv_integer(unsigned(target))) then --timer limit has been reached
LD0 <= '1';
else
counter := counter + 1;
display_counter := display_counter + 1;
if(counter rem 10 = 0) then --one second has elapsed (10Hz cycle)
timer := timer + 1; --increase timer
end if;
case display_counter is --Select which digits are gonna be activated and with what
when 1 =>
seg <= int2led(timer/1000);
if(int2led(timer/1000) = "00000000") then
digit(3) <= '1';
else
digit(3) <= '0';
end if;
when 2 =>
seg <= int2led((timer/100) mod 10);
if(int2led((timer/100) mod 10) = "00000000") then
digit(2) <= '1';
else
digit(2) <= '0';
end if;
when 3 =>
seg <= int2led((timer/10) mod 10);
if(int2led((timer/10) mod 10) = "00000000") then
digit(1) <= '1';
else
digit(1) <= '0';
end if;
when others =>
seg <= int2led(timer/10);
if(int2led(timer/10) = "00000000") then
digit(1) <= '1';
else
digit(1) <= '0';
end if;
end case;
if (display_counter = 4) then --reset the display counter from time to time
display_counter := 0;
else
display_counter := display_counter;
end if;
end if;
end if;
end process;
end Behavioral;
The problem is at if(rst='1') then. Can anyone explain to me in plain English why is this happening and a solution to it so I won't have the same kind problems again? Thanks in advance
You have default signal assignments before the if rst='1' then clause.
That means, when rst returns to 0 (in simulation) these default assignments will execute, and delete the reset values of those signals.
XST is telling you that the hardware can't actually do that.
The solution is to delete those default assignments, which will restore this process to a standard form. Then think carefully about what they were for and how to keep their functionality if you need to.
The traditional place for such assignments is immediately after the elsif rising_edge(clk) then clause, where they will be executed on every clock edge (provided Rst is low) then overridden by any other assignments that are executed yb the process.
I am trying to implement a few "ball" bouncing around on a 800x600 screen. I dont completely understand how to make the 2nd ball move on the screen. Right now, it just stays on the screen statically at a certain position.
Here is a shot at what I've done so far.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pong is
Port ( myclk : in STD_LOGIC;
rgb : out STD_LOGIC_VECTOR (2 downto 0);
hs : out STD_LOGIC;
vs : out STD_LOGIC);
end pong;
architecture Behavioral of pong is
signal clk: STD_LOGIC;
signal horz_scan: STD_LOGIC_VECTOR (9 downto 0);
signal vert_scan: STD_LOGIC_VECTOR (9 downto 0);
signal vinc_flag: STD_LOGIC;
signal dx: STD_LOGIC;
signal dy: STD_LOGIC;
signal refresh_counter: STD_LOGIC;
signal posx: integer := 300;
signal posy: integer := 300;
signal color: STD_LOGIC_VECTOR (2 downto 0) := "111";
signal vinc_flag2: STD_LOGIC;
signal dx2: STD_LOGIC;
signal dy2: STD_LOGIC;
signal posx2: integer := 300;
signal posy2: integer := 300;
signal color2: STD_LOGIC_VECTOR (2 downto 0) := "001";
signal refresh_counter2: STD_LOGIC;
signal horz_scan2: STD_LOGIC_VECTOR (9 downto 0);
signal vert_scan2: STD_LOGIC_VECTOR (9 downto 0);
signal clk2: STD_LOGIC;
begin
-- Clock divide by 1/2
process(myclk)
begin
if myclk = '1' and myclk'Event then
clk <= not clk;
end if;
end process;
-- horizonal clock
process(clk)
begin
if clk = '1' and clk'Event then
if horz_scan = "1100100000" then
horz_scan <= "0000000000";
else
horz_scan <= horz_scan + 1;
end if;
end if;
end process;
-- vertial clock (increments when the horizontal clock is on the front porch
process(vinc_flag)
begin
if vinc_flag = '1' and vinc_flag'Event then
if vert_scan = "1000001001" then
vert_scan <= "0000000000";
refresh_counter <= refresh_counter xor '1';
else
vert_scan <= vert_scan + 1;
end if;
end if;
end process;
process(vinc_flag2)
begin
if vinc_flag2 = '1' and vinc_flag2'Event then
if vert_scan2 = "1000001001" then
vert_scan2 <= "0000000000";
refresh_counter2 <= refresh_counter2 xor '1';
else
vert_scan2 <= vert_scan2 + 1;
end if;
end if;
end process;
process(refresh_counter)
begin
if refresh_counter = '1' and refresh_counter'Event then
if dx = '0' then
posx <= posx + 1;
else
posx <= posx -1;
end if;
if dy = '0' then
posy <= posy + 1;
else
posy <= posy -1;
end if;
color <= "100";
end if;
end process;
process(refresh_counter2)
begin
if refresh_counter2 = '1' and refresh_counter2'Event then
if dx2 = '0' then
posx2 <= posx2 + 1;
else
posx2 <= posx2 -1;
end if;
if dy2 = '0' then
posy2 <= posy2 + 1;
else
posy2 <= posy2 -1;
end if;
color2 <= "001";
end if;
end process;
process(posx)
begin
if posx = 144 then
dx <= '0';
elsif posx = 734 then
dx <= '1';
end if;
end process;
process(posy)
begin
if posy = 35 then
dy <= '0';
elsif posy = 465 then
dy <= '1';
end if;
end process;
process(posx2)
begin
if posx = 144 then
dx <= '0';
elsif posx = 734 then
dx <= '1';
end if;
end process;
process(posy2)
begin
if posy = 35 then
dy <= '0';
elsif posy = 465 then
dy <= '1';
end if;
end process;
-- horizontal sync for 96 horizontal clocks (96 pixels)
hs <= '1' when horz_scan < 96 else '0';
-- vertial sync for 2 scan lines
vs <= '1' when vert_scan(9 downto 1) = "000000000" else '0';
rgb <= color when (vert_scan >= posy and vert_scan < (posy+50) and horz_scan >= posx and horz_scan < posx+50) or (vert_scan >= posy2 and vert_scan < (posy2+50) and horz_scan >= posx2 and horz_scan < (posx2+50)) else "000";
vinc_flag <= '1' when horz_scan = "1100011000" else '0';
end Behavioral;
There seems to be a copy and paste error in your code. The last two processes are sensitive to posx2 and posy2 respectively, but you seem to be changing the state of the first ball (dx and dy). Shouldn't you be changing dx2 and dy2 instead?
Also, here are two suggestions to make your code more readable:
Instead of declaring your counters as std_logic_vectors and comparing them against bit-string literals (e.g., if vert_scan2 = "1000001001" then ...), why not declare the counters as integers? That would contribute to making you code more readable.
Don't use "magic numbers" or hardcoded literals spread throughout your code (e.g., in the expression if posx = 144 then ..., 144 is a magic number). Instead, create a constant with a meaningful name (constant BALL_X_POS_MIN: integer := 144;) and use it in your expressions (if posx = BALL_X_POS_MIN then ...).