Make file command not executed in windows console - makefile

I am using makefile to build my code for boost cpp application. When makefile get executed it shows following message
g++ -c -Wall -I/c/MinGW/include/ -lboost_system -lws2_32 Timer_async.cpp -o Timer_async.o
and throws following error
#include <boost/asio.hpp>
^
compilation terminated.
mingw32-make: *** [makefile:15: Timer_async.o] Error 1
but if I run this makefile generated command from shell prompt
g++ -c -Wall -I/c/MinGW/include/ -lboost_system -lws2_32 Timer_async.cpp -o Timer_async.o
Program builds properly.
My make file is as
CC=g++
CFLAGS=-c -Wall
LDFLAGS=-lboost_system -lws2_32
INCLUDES=-I/c/MinGW/include/
SOURCES=Timer_async.cpp
OBJECTS=$(SOURCES:.cpp=.o)
EXECUTABLE=hello
all: $(SOURCES) $(EXECUTABLE)
$(EXECUTABLE): $(OBJECTS)
$(CC) $(SOURCES) $(INCLUDES) $(LDFLAGS) -o $#
.cpp.o:
$(CC) $(CFLAGS) $(INCLUDES) $(LDFLAGS) $< -o $#

I think the error is may be how conemu handles file paths. after changing make file to following more specific
CFLAGS = -c -I/c/MinGW/include
2
3 hello: Timer_async.o
4
5 Timer_async.o: Timer_async.cpp
6 g++ $(CFLAGS) Timer_async.cpp
7
8 clean:
9 rm Timer_async.o
I was still getting errors but after adding double quotes in path all errors were corrected.
My modified make file is
CFLAGS = -c -I"/c/MinGW/include"
2
3 hello: Timer_async.o
4
5 Timer_async.o: Timer_async.cpp
6 g++ $(CFLAGS) Timer_async.cpp
7
8 clean:
9 rm Timer_async.o

Why do you specify both $(SOURCES) and $(EXECUTABLE) as dependencies to all? What is that adding that the $(EXECUTABLE) rule isn't achieving?
The #include is failing (that's what the diagnostic message seems to indicate) because the target file cannot be found. You have used the -I flag incorrectly. That will only influence how includedFile.c is located; it has no effect on <includedFile.c>.
Your conclusion "Makefile command not executed" (and I have no idea what a "Makefile command" is) was unwarranted. make did exactly what it was supposed to.

Related

Makefile add last flag

I am trying to compile my project using makefile.
Command line that works perfectly for me is:
g++ -I stuff/ -L stuff2/ src/Core.cpp -o file_name -ljvm
If I miss -ljvm at the end I end up with an error while compiling, this flag must go after file_name. The problem is that I am unable to add -ljvm successfully using makefile.
My makefile looks like this:
NAME = 'AI'
SRC = src
TGT = obj
PRG = application
INCLUDES = -Iinclude -I /usr/lib/jvm/java-7-openjdk-amd64/include/
LIBRARIES = -L /usr/lib/jvm/java-7-openjdk-amd64/jre/lib/amd64/server/
CXXFLAGS = -Wall -O3 -std=c++0x $(INCLUDES) $(LIBRARIES)
SOURCES = $(wildcard $(SRC)/*.cpp)
OBJS = $(addprefix $(TGT)/, $(notdir $(SOURCES:.cpp=.o)))
$(TGT)/%.o: $(SRC)/%.cpp
$(CXX) $(CXXFLAGS) -c $< -o $#
$(PRG)/$(NAME): $(OBJS)
$(CXX) $(LDFLAGS) $(OBJS) -o $#
Which gives me an error since I have not added -ljvm.
If I add it to: $(CXX) $(CXXFLAGS) -c $< -o $# -ljvm, nothing changes and I still get same error.
If I add it to last line $(CXX) $(LDFLAGS) $(OBJS) -o $# -ljvm I get a different error:
g++ obj/Core.o -o application/'AI' -ljvm
/usr/bin/ld: cannot find -ljvm
collect2: error: ld returned 1 exit status
make: *** [application/'AI'] Error 1
I have a feeling that I am missing something simple here. Any suggestions are much appreciated.
Your last line uses $(LDFLAGS) that is actually never defined.
ld complains about the fact it cannot find -ljvm, that's because you have to pass
-L /usr/lib/jvm/java-7-openjdk-amd64/jre/lib/amd64/server/
to the linker (i.e. add it to your last command).
Try defining LDFLAGS with, at least, $(LIBRARIES) in it.

How to run the targets parallely in makefile

I have a makefile :
CC=g++
CFLAGS=-c -Wall
LDFLAGS=
SOURCES=main.cpp hello.cpp factorial.cpp
OBJECTS=$(SOURCES:.cpp=.o)
EXECUTABLE=hello
all: $(EXECUTABLE)
$(EXECUTABLE): $(OBJECTS)
$(CC) $(LDFLAGS) $(OBJECTS) -o $#
%.o: %.cpp
$(CC) $(CFLAGS) $(<F) -o $#
When we execute this, we can see that the targets main.o, hello.o, factorial.o are running in serial, as these are independent of each, can we make them to run in parallel.
g++ -c -Wall main.cpp -o main.o
g++ -c -Wall hello.cpp -o hello.o
g++ -c -Wall factorial.cpp -o factorial.o
If yes, please help me
(Answered in a comment. See: Empty InfoWindow when Marker is clicked )
#Wintermute wrote:
Call make -j $number, where $number is the maximum number of processes you want it to spawn in parallel.
See also the documentation here: https://www.gnu.org/software/make/manual/html_node/Parallel.html#Parallel

Makefile error, can't resolve include

I'm working with a project using flex/bison and trying to compile it using make. The lex.yy.c, tab.c, tab.h from flex/bison are generated correctly and placed in the obj directory. However, there is an error when trying to compile the obj/lex.yy.c file and it cannot resolve an include to a file in the src/frontend directory. Any ideas where I am going wrong? Makefile and output included below.
Makefile:
VPATH = src obj src/frontend src/interpreter
SRCS = lex.yy.c C.tab.c symbol_table.c nodes.c print_ast.c interpreter.c main.c
OBJS := $(SRCS:%.c=obj/%.o)
INCLUDES = -Isrc -Iobj -Isrc/frontend -Isrc/interpreter
CPPFLAGS = -Wall
LDFLAGS = -Wall
CC = gcc
LEX = flex
YACC = bison -d -t -v
all: bin/mycc
bin/mycc: $(OBJS)
$(CC) -g $(LDFLAGS) $(INCLUDES) -o $# $^
obj/lex.yy.c: C.flex obj/C.tab.h
$(LEX) -o $# $<
obj/C.tab.c: C.y
$(YACC) -o $# $<
obj/C.tab.h: obj/C.tab.c
#touch $#
obj/%.o: src/%.c
$(CC) -g $(CPPFLAGS) $(INCLUDES) -c $^
clean:
rm $(OBJS) obj/lex.yy.c obj/C.tab.c obj/C.tab.h
depend:
$(CC) -M $(SRCS) > .deps
cat Makefile .deps > makefile
Output:
bison -d -t -v -o obj/C.tab.c src/frontend/C.y
src/frontend/C.y: conflicts: 4 shift/reduce, 14 reduce/reduce
src/frontend/C.y:248.11-53: warning: rule useless in parser due to conflicts: external_declaration: function_definition
flex -o obj/lex.yy.c src/frontend/C.flex
gcc -Wall -c -o obj/lex.yy.o obj/lex.yy.c
src/frontend/C.flex:13:19: fatal error: token.h: No such file or directory
#include "token.h"
^
compilation terminated.
make: *** [obj/lex.yy.o] Error 1
The problem is that you define your -I flags for compiling in the variable $(INCLUDES) instead of in the normal $(CPPFLAGS). As a result, when the default rule for compiling C files runs, it does not use any of those -I flags and so the compiler can't find the include files. You can see the command line for the compiler in your output.
To fix it, get rid of the INCLUDES = line and add all of them to CPPFLAGS:
CPPFLAGS = -Wall -Isrc -Iobj -Isrc/frontend -Isrc/interpreter

Problems wih make file code

When i run the code below , it give me an error message which is :
cc1: warning: main.c: not a directory [enabled by default]
frequent.o: file not recognized: File format not recognized
collect2: error: ld returned 1 exit status
make: * [main] Error 1
CC = gcc
CPPFLAGS = -I
main: main.c headers.h sortt.o frequent.o
#$(CC) $(CPPFLAGS) -c $^ -o $#
sortt.o: headers.h sortt.c
$(CC) $(CPPFLAGS) -c $< -o $#
frequent.o: headers.h frequent_word.c search_similar_word.o
$(CC) $(CPPFLAGS) -c $< -o $#
You have a lot of errors in your rules. Why is frequent.o listing search_similar_word.o as a prerequisite? There's no reason that you can't build frequent.o before or at the same time as search_similar_word.o.
Also, you are using $< in the compilation line which expands to the first prerequisite, but the first prerequisite for frequent.o is headers.h, so you're trying to compile headers.h which is wrong: you want to compile frequent_word.c.
Ditto for sortt.o.
It's also very odd to name your object files with different names than the source files.
In your CPPFLAGS you're listing a -I flag but you've given it no argument: that flag takes a directory as an argument.
And finally, you are using the -c flag when you're trying to link the final object (I'm assuming the comment character # is just an artifact of debugging); that's not right as the -c flag tells the compiler to generate an object file, and to not link the final object.
Your makefile should look something like this:
CC = gcc
CPPFLAGS = -I .
main: main.c headers.h sortt.o frequent.o
$(CC) $(CPPFLAGS) $^ -o $#
sortt.o: sortt.c headers.h
$(CC) $(CPPFLAGS) -c $< -o $#
frequent.o: frequent_word.c headers.h
$(CC) $(CPPFLAGS) -c $< -o $#
I have no idea what to do with search_similar_word.o since it doesn't seem to be used anywhere in your build.

make: No targets. Stop

make is working strangely on my Makefile. It gives error "No targets. Stop". When I write make clean, it writes: "No rule to make target clean."
If i compile each file separately everything is fine.
Below is the code:
CC = g++
CFLAGS = -g -Wall
BOOSTIP = -I path/to/boost
default: abc
all: abc
abc: main.o node.o network.o my_funs.o my_random.o
$(CC) $(CFLAGS) $(BOOSTIP) main.o node.o network.o my_funs.o my_random.o -o abc
main.o: main.cpp node.hpp network.hpp
$(CC) $(CFLAGS) $(BOOSTIP) main.cpp -o main.o
node.o: node.cpp node.hpp my_funs.hpp my_random.hpp
$(CC) $(CFLAGS) $(BOOSTIP) node.cpp -o node.o
network.o: network.cpp network.hpp node.hpp my_funs.hpp my_random.hpp
$(CC) $(CFLAGS) $(BOOSTIP) network.cpp -o network.o
my_funs.o: my_funs.cpp my_funs.hpp node.hpp my_random.hpp
$(CC) $(CFLAGS) $(BOOSTIP) my_funs.cpp -o my_funs.o
my_random.o: my_random.cpp my_random.hpp
$(CC) $(CFLAGS) $(BOOSTIP) my_random.cpp -o my_random.o
clean:
rm abc *.o *~
The error was due to bad line ending. Makefile had only CR, as it should have LF.
Correcting it solved the problem.
I got this error several times and in many of these cases the error was very simple, some space left after the value attributed to a variable, for an instance in make book where book: was the label of a sequence to LaTeX my book "name" in the attribution field have written "text=name ". Solution: "text=name" no spaces left behind name. Now I do define variables putting the sign of comment just at the end
to prevent this error: "text=name##"

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