make: No targets. Stop - makefile

make is working strangely on my Makefile. It gives error "No targets. Stop". When I write make clean, it writes: "No rule to make target clean."
If i compile each file separately everything is fine.
Below is the code:
CC = g++
CFLAGS = -g -Wall
BOOSTIP = -I path/to/boost
default: abc
all: abc
abc: main.o node.o network.o my_funs.o my_random.o
$(CC) $(CFLAGS) $(BOOSTIP) main.o node.o network.o my_funs.o my_random.o -o abc
main.o: main.cpp node.hpp network.hpp
$(CC) $(CFLAGS) $(BOOSTIP) main.cpp -o main.o
node.o: node.cpp node.hpp my_funs.hpp my_random.hpp
$(CC) $(CFLAGS) $(BOOSTIP) node.cpp -o node.o
network.o: network.cpp network.hpp node.hpp my_funs.hpp my_random.hpp
$(CC) $(CFLAGS) $(BOOSTIP) network.cpp -o network.o
my_funs.o: my_funs.cpp my_funs.hpp node.hpp my_random.hpp
$(CC) $(CFLAGS) $(BOOSTIP) my_funs.cpp -o my_funs.o
my_random.o: my_random.cpp my_random.hpp
$(CC) $(CFLAGS) $(BOOSTIP) my_random.cpp -o my_random.o
clean:
rm abc *.o *~

The error was due to bad line ending. Makefile had only CR, as it should have LF.
Correcting it solved the problem.

I got this error several times and in many of these cases the error was very simple, some space left after the value attributed to a variable, for an instance in make book where book: was the label of a sequence to LaTeX my book "name" in the attribution field have written "text=name ". Solution: "text=name" no spaces left behind name. Now I do define variables putting the sign of comment just at the end
to prevent this error: "text=name##"

Related

How to let avr-gcc output *.o to separate folder in Makefile with `%.o: %.c`?

As showed in first screenshot, my ideal AVR project structure is that:
*.o, *.elf and *.hex files are in build folder.
PomoScheler.c and pinDefines.h as main files are in root folder, while other *.c and *.h are in src folder.
But *.o are always generated at the same folder as *.c like showed in second screenshot, no matter how.
(I attached my endeavors and whole Makefile below the screenshots)
Firstly, I tried build/ before $#, in vain. The terminal still the same.
# My first Makefile endeavor
%.o: %.c $(HEADERS)
$(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o build/$#
# Terminal command generated by Makefile (Look at the end: *.o path still same as *.c)
avr-gcc -Os -g -std=gnu99 -Wall -funsigned-char -funsigned-bitfields -fpack-struct -fshort-enums -ffunction-sections -fdata-sections -DF_CPU=1000000UL -DBAUD=9600UL -I. -I~/Developer/bin/avr8-gnu-toolchain-darwin_x86_64/avr/include -mmcu=atmega328p -c -o src/RotaryEncoder.o src/RotaryEncoder.c
Secondly, I tried to add mv $# build to explicitly move it to build folder. But nothing happened. Even echo are not displayed in Terminal.
# My second Makefile endeavor
%.o: %.c $(HEADERS)
$(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $#
mv $# build
echo ---------Hello---------
Thirdly, I delete $(HEADERS) and replace $< with $^ just to have a try. The mv is executed. But it cannot find *.o file this time even though I have VPATH = src:build in Makefile.
# My third Makefile endeavor
%.o: %.c
$(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c $^ -o $#
mv $# build
# Terminal error
Assembler messages:
Fatal error: can't create build/src/RotaryEncoder.o: No such file or directory
And my whole Makefile is here. Please help me out.
# My whole Makefile
MCU = atmega328p
F_CPU = 1000000UL
BAUD = 9600UL
LIBDIR = ~/Developer/bin/avr8-gnu-toolchain-darwin_x86_64/avr/include
PROGRAMMER_TYPE = usbtiny
PROGRAMMER_ARGS =
CC = avr-gcc
OBJCOPY = avr-objcopy
OBJDUMP = avr-objdump
AVRSIZE = avr-size
AVRDUDE = avrdude
##########------------------------------------------------------##########
VPATH = ./src:./build
TARGET = $(lastword $(subst /, ,$(CURDIR)))
SOURCES=$(wildcard *.c src/*.c $(LIBDIR)/*.c)
OBJECTS=$(SOURCES:.c=.o)
HEADERS=$(SOURCES:.c=.h)
CPPFLAGS = -DF_CPU=$(F_CPU) -DBAUD=$(BAUD) -I. -I$(LIBDIR)
CFLAGS = -Os -g -std=gnu99 -Wall
CFLAGS += -funsigned-char -funsigned-bitfields -fpack-struct -fshort-enums
CFLAGS += -ffunction-sections -fdata-sections
LDFLAGS = -Wl,-Map,build/$(TARGET).map
LDFLAGS += -Wl,--gc-sections
TARGET_ARCH = -mmcu=$(MCU)
%.o: %.c $(HEADERS)
$(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o build/$#
$(TARGET).elf: $(OBJECTS)
$(CC) $(LDFLAGS) $(TARGET_ARCH) $^ $(LDLIBS) -o build/$#
%.hex: %.elf
$(OBJCOPY) -j .text -j .data -O ihex build/$< build/$#
all: $(TARGET).hex
size: $(TARGET).elf
$(AVRSIZE) -C --mcu=$(MCU) $(TARGET).elf
clean:
rm -f $(TARGET).elf $(TARGET).hex $(TARGET).obj \
$(TARGET).o $(TARGET).d $(TARGET).eep $(TARGET).lst \
$(TARGET).lss $(TARGET).sym $(TARGET).map $(TARGET)~ \
$(TARGET).eeprom
flash: $(TARGET).hex
$(AVRDUDE) -c $(PROGRAMMER_TYPE) -p $(MCU) $(PROGRAMMER_ARGS) -U flash:w:$<
This is clearly not right:
OBJECTS = $(SOURCES:.c=.o)
because the object files you want to create are not foo.o etc. which is what this will expand to; the object files are build/foo.o etc. So this has to be:
OBJECTS = $(patsubst %.c,build/%.o)
All of your attempts to trick make by telling it your recipe will build one target (foo.o) but actually building a totally different target (build/foo.o) are doomed to fail, regardless of whether you have the compiler do it directly, you use mv, or any other method.
If you just tell make what your recipe actually does, you will have a much simpler time of it:
build/%.o: %.c
mkdir -p $(#D)
$(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c $^ -o $#
Probably you have similar issues with the other rules that you want to put into other directories.
You can't do this by trying to hide it from make. Make has to know where the files actually are.
BTW, VPATH cannot help here. VPATH is for finding source files, it cannot be used for finding generated files. So you could use VPATH to find your .c files but not your .o files.

Makefile - Compile Single Objects in different directory

I have been combing the web and I can't figure out the right way to get this to work. Just trying to create a simple Makefile which takes my source and only builds the changed files. I need all the .o files to be put in the same output folder. I currently have everything working except that if I change one file the whole thing rebuilds. For example, if I change main.c it will compile EOL.c as well. However if nothing changes it says nothing needs to be done.
NAME=Program
CC=arm-none-eabi-gcc
CFLAGS=-c -Wall -O0 -std=c99 \
-nostartfiles --specs=nano.specs \
-mthumb -fmessage-length=0 \
-fsigned-char -ffunction-sections \
-fdata-sections -mcpu=cortex-m0
BID?=_DEV
DEFINES= -DPROD -DBLD_ID=\"$(BID)\"
LDFLAGS= -nostartfiles
INCLUDES= -ISrc/App/Include -ISrc/Device/CMSIS/Include
SOURCES= Src/main.c Src/App/Source/Application.c Src/App/Source/EOL.c Src/Svc/Source/TimerManager.c
OBJECTS=$(OBJECTS1:.c=.o)
OBJECTS1=$(SOURCES:.S=.o)
OFILES1=$(notdir ${OBJECTS})
OFILES=$(addprefix $(OBJDIR)/,$(OFILES1))
OBJDIR=Output
.PHONY: all rebuild clean
all: $(OBJDIR) $(SOURCES) $(OBJDIR)/$(NAME).hex
%.hex: %.elf
arm-none-eabi-objcopy -O ihex $< $#
%elf: $(OBJECTS)
$(CC) $(LDFLAGS) $(OFILES) -o $#
rebuild: clean all
.SECONDARY:
.c.o:
$(CC) $(CFLAGS) $(DEFINES) $(INCLUDES) $< -o $(OBJDIR)/$(notdir $#)
.S.o:
$(CC) $(CFLAGS) $(DEFINES) $(INCLUDES) $< -o $(OBJDIR)/$(notdir $#)
$(OBJDIR):
mkdir $(OBJDIR)
clean:
rm -f $(OBJDIR)/*.o $(OBJDIR)/*.elf $(OBJDIR)/*.hex $(OBJDIR)/*.bin
There are several problems with this makefile. Basically you have rules whose targets are not the files they actually produce, and a rule whose prerequisites are not the files it actually needs.
Suppose you have modified Src/main.c and try to rebuild Output/Program.elf using this rule:
%elf: $(OBJECTS)
$(CC) $(LDFLAGS) $(OFILES) -o $#
The prerequisites ($(OBJECTS)) are actually Src/main.o Src/App/Source/EOL.o and so on. These files do not exist -- they never exist -- but there is a rule for them:
.c.o:
$(CC) $(CFLAGS) $(DEFINES) $(INCLUDES) $< -o $(OBJDIR)/$(notdir $#)
Make sees that Src/main.o depends on Src/main.c and must therefore be rebuilt, as must Output/Program.elf. So it invokes this rule -- which actually builds Output/main.o. But the elf rule demands all of the (imaginary) object files, so all of the sources must be recompiled-- into object files that already exist and are not out of date, but which Make wasn't paying attention to.
The first thing to do is fix the object rules, but there's a problem: although the rules are flawed, they have the advantage of helping Make to find the corresponding source files (before misusing them), like this:
Src/App/Source/EOL.o: Src/App/Source/EOL.c
...
How can we tell Make where to find the source file corresponding to Output/EOL.o? There's more than one way, but a good way is by using vpath:
vpath %.c Src/App/Source
Output/EOL.o: EOL.c
...
All we have to do is create a list of source directories, pass it to vpath, and modify the pattern rule:
SRCDIRS := $(dir $(SOURCES))
vpath %.c $(SRCDIRS)
$(OBJDIR)/%.o: %.c
$(CC) $(CFLAGS) $(DEFINES) $(INCLUDES) $< -o $#
(The .S.o rule can be fixed the same way.)
Then modify the elf rule to name -- and use -- its real prerequisites:
%elf: $(OFILES)
$(CC) $(LDFLAGS) $^ -o $#

Makefile executable not generated

CC=g++
CFLAGS=-c -o
PROG=craps
LIBSRCS=craps.cpp craps_game.cpp craps_helper.cpp craps_io.cpp
LIBOBJS=$(patsubst %.cpp, %.o, $(LIBSRCS))
LIBCRAPS=craps
CXXFLAGS=-I./ -fpic
LDFLAGS=-L./
all: $(PROG)
$(PROG): $(LIBSRCS)
$(CC) $(LDFLAGS) -l$(PROG) -o $(PROG) $(PROG).o
$(LIBCRAPS): $(LIBOBJS)
$(CC) -shared -o lib$(LIBCRAPS).so $(LIBOBJS)
%.o: %.cpp
$(CC) $(CXXFLAGS) -c -o $# $
depend:
${CC} -MM ${PROG}.cpp ${LIBSCRS} > depends.mak
include depends.mak
Why executable file not compiled and generated?
All o files generated with no error.
Why this line $(CC) $(LDFLAGS) -l$(PROG) -o $(PROG) $(PROG).o does not run ? what is wrong ?
You misunderstood my comment. I'm saying this this:
PROG=craps LIBSRCS=craps.cpp craps_game.cpp craps_helper.cpp craps_io.cpp
is wrong. You can't assign two variables on the same line, in a makefile. These variables must look like this:
PROG=craps
LIBSRCS=craps.cpp craps_game.cpp craps_helper.cpp craps_io.cpp
I'm asking, is the latter how your actual makefile looks, or is the example you provided here just inaccurate.
Also these rules both have incorrect newlines:
$(PROG):
$(LIBSRCS) $(CC) $(LDFLAGS) -l$(PROG) -o $(PROG) $(PROG).o
$(LIBCRAPS):
$(LIBOBJS) $(CC) -shared -o lib$(LIBCRAPS).so $(LIBOBJS)
You are adding the prerequisite lists $(LIBSRCS) and $(LIBOBJS) into the recipe (shell commands) used to build the target. Prerequisites must be on the same line as the target. These should look like this:
$(PROG): $(LIBSRCS)
$(CC) $(LDFLAGS) -l$(PROG) -o $(PROG) $(PROG).o
$(LIBCRAPS): $(LIBOBJS)
$(CC) -shared -o lib$(LIBCRAPS).so $(LIBOBJS)
This is your problem, below
Finally, you can't have both the program and the target have the same name:
PROG=craps
LIBCRAPS=craps
You can only create one target with a given name so the value of both these variables cannot be craps. Maybe you wanted:
PROG = craps
LIBCRAPS = libcraps.so
Assuming the makefile you've quoted here is identical to what you're running, you must be getting warnings like this from make when you run this makefile:
Makefile:15: warning: overriding recipe for target 'craps'
Makefile:12: warning: ignoring old recipe for target 'craps'
These warnings are why you are not seeing the compile rule invoked: the library rule is overriding it just as the warning says.
Also, you should have the program depend on the library (since it links it) and the object file $(PROG).o because currently make doesn't know it needs to be built. And you don't need to have it depend on all the source files. You want something like:
$(PROG): $(LIBCRAPS) $(PROG).o
$(CC) $(LDFLAGS) -l$(PROG) -o $(PROG) $(PROG).o

How to write a makefile for llvm IR

If I have 3 files, function.h, function.c and my_program.c which calls a method in function.h all in the same directory, what would be the best way to write a makefile so that I end up with a my_program.bc that would actually run when I type in lli my_program.bc? (I need to run a user defined pass that would insert stuff into the functions - should I run the pass on function.bc and test.bc, or should I link before running the pass?)
I've tried llvm-link function.bc my_program.bc with no luck. I feel I'm either missing something simple or going about the whole thing wrong.
Current terrible none-working makefile:
.PHONY: all clean
CC = clang
CFLAGS = -std=gnu99 -D_POSIX_C_SOURCE=200809L -g -Wall
IRFLAGS = -O3 -emit-llvm
TARGET = test
DEPS = functions.h
all: $(TARGET)
bc: test2
%.o: %.c $(DEPS)
$(CC) -c -o $# $< $(CFLAGS)
%.bc: %.c $(DEPS)
$(CC) $(IRFLAGS) -c -o $# $<
test2: test.bc functions.bc
llvm-link -o test2.bc $< functions.bc
test: test.o functions.o
$(CC) $(CFLAGS) -o $# $^
clean:
$(RM) $(TARGET) *.o *.bc
Why not just write a normal Makefile to produce the desired executable,
then use wllvm?
Shameless plug for wllvm:
https://github.com/SRI-CSL/whole-program-llvm
I do not use lli, so I would be interested to hear about how it resolved
any reliance on stdlibc that your program may have.

variable error in makefile

I have Makefile in Ubuntu12.10 as below.
when I run it by make command, it shows as
g++ -c -o myprog1.o myprog1.cpp
It seems the variables CFLAGS and CINCLUDE do not work.
Can any one help me to check it?
Thanks,
RM = rm -f
CC = gcc
AR = ar rc
CFLAGS= -Wall -g -O2 -std=c++11 -fPIC
CINCLUDE= -I. -I../include
OBJECTS= myprog1.o myprog2.o
STATIC_LIB = libctest.a
$(STATIC_LIB): $(OBJECTS)
$(AR) $(STATIC_LIB) $(OBJECTS)
%.o : %.c
$(CC) -c $(CFLAGS) $(CINCLUDE) $< -o $#
clean:
$(RM) $(OBJECTS)
$(RM) $(STATIC_LIB)
The problem is that you have a make rule for %.o : %.c but not for %.o : %.cpp. When you run the make, the implicit make rule for '%.cpp' runs, but the implicit rule doesn't contain references to CFLAGS or CINCLUDE.
Since your source is in c++, you probably want to add another rule for c++ compilation and set up the CXX variables appropriately.
CXXFLAGS = $(CFLAGS)
%.o : %.cpp
$(CXX) -c $(CXXFLAGS) $(CINCLUDE) $< -o $#

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