I am following this tutorial and I have gotten to the point where I need to 'make' compiled image to get it into pi, but I am getting following error:
mkdir build/
The syntax of the command is incorrect.
Makefile:57: recipe for target 'build/' failed
mingw32-make: *** [build/] Error 1
The makefile is available here in the template. Lines 56 + 57 look like this:
$(BUILD):
mkdir $#
Can anyone tell me what's wrong and how to fix it? I am new to this and following the step by step guide :/ Thank you!
Thanks to igagis' coment I have discovered what the problem was that: mkdir build/ is incorrect command because of the slash sign '/'.
In the make file, the variable target is defined as: BUILD = build/ because it is later used as a path. I fixed line 57 as following:
$(BUILD):
mkdir build
and the code now compiles as intended.
Related
I am having trouble with the following code.
CFG_PATH := cfg_path
include ${CFG_PATH}/makefile.cfg
INPUT_DIR=${PROG_INPUT_DIR}/input
MANIFEST_FILE = ${MANIFEST_DIR}/manifest.xml
$(shell mkdir -p ${INPUT_DIR})
Some_Target:
.
.
.
.
Target:
When I call this makefile from another makefile it is failing at the include line and I get the following error
ERROR: ${CFG_PATH}/makefile.cfg no such file or directory found.
In our current system, this code work fine as is and it executes fine but when I try to call it from another makefile it fails and I get that error
How I am calling the makefile.
${MAKE} Target -f ${makefile_location}/makefile
Thanks in advance!
I'm trying to compile this project from DTU. This project requires that PETSc be installed.
I have installed PETSc to /Users/hornymoose/petsc-3.13.3/
I have extracted the zip from GitHub to /Users/hornymoose/dtu
The DTU project's makefile has the following lines:
include ${PETSC_DIR}/lib/petsc/conf/variables
include ${PETSC_DIR}/lib/petsc/conf/rules
include ${PETSC_DIR}/lib/petsc/conf/test
In these lines, {PETSC_DIR} is to be substituted with the user's PETSc installation directory. Thus, I changed these lines to:
include $/Users/hornymoose/petsc-3.13.3/lib/petsc/conf/variables
include $/Users/hornymoose/petsc-3.13.3/lib/petsc/conf/rules
include $/Users/hornymoose/petsc-3.13.3/lib/petsc/conf/test
To compile the code, I write make topopt in Terminal. Doing so yields:
makefile:13: Users/hornymoose/petsc-3.13.3/lib/petsc/conf/variables: No such file or directory
makefile:14: Users/hornymoose/petsc-3.13.3/lib/petsc/conf/rules: No such file or directory
makefile:15: Users/hornymoose/petsc-3.13.3/lib/petsc/conf/test: No such file or directory
make: *** No rule to make target `Users/jhutopopt/petsc-3.13.3/lib/petsc/conf/test'. Stop.
I have gone back and manually checked that Users/hornymoose/petsc-3.13.3/lib/petsc/conf/variables, ...rules, and ...test definitely exist and do not have errors.
Why am I receiving this error? Am I indicating the directory incorrectly in my makefile? Is the syntax in the makefile incorrect?
I'm sure there is a simple solution, I'm just very new to working with Terminal in MacOS. Thank you in advance!
There is a $ in the paths:
include $/Users/hornymoose/petsc-3.13.3/lib/petsc/conf/variables
^
This causes the / to be treated as a variable, and expanded to nothing because was never set. Run make with option --warn-undefined-variables to get a warning on that sort of thing. Perhaps already obvious at this point, but the correct line would be:
include /Users/hornymoose/petsc-3.13.3/lib/petsc/conf/variables
Rather than manually substituting the PETSC_DIR in the makefile you can provide it through an environment variable (assuming PETSc makefiles aren't bad):
export PETSC_DIR=/Users/hornymoose/petsc-3.13.3
make topopt
...or:
PETSC_DIR=/Users/hornymoose/petsc-3.13.3 make topopt
...or pass its value to the make invocation:
make topopt PETSC_DIR=/Users/hornymoose/petsc-3.13.3
I just made this test driver using AOSP kernel "https://android.googlesource.com/kernel/common"
I put my driver code "tdrive", under "common/drivers", in which contains 2 files "Makefile" and "hello_kernel.c"
I also added my module in the common/drivers/Makefile as obj-y
After I type "./build/build.sh"
I got build error as
make: *** [/work/android/aosp/repo-db845c/common/Makefile:185: __sub-make] Error 2
Nothing else for the error, I have no clue but open the makefile mentioned above, at the line 185 it looks like:
183 # Invoke a second make in the output directory, passing relevant variables
184 __sub-make:
185 $(Q)$(MAKE) -C $(abs_objtree) -f $(abs_srctree)/Makefile $(MAKECMDGOALS)
Anyone can tell where should I go to find my errors? Thanks!
PS - I also tried with
./build/build.sh -d
I am trying to run https://github.com/pavanpongle/IoT-Wormhole-IDS. After following README.md and Instructions to run, I understood that I need to use the Makefile. I have properly indented the file which now looks as below:
DEFINES+=PROJECT_CONF_H=\"project-conf.h\"
all:$(CONTIKI_PROJECT)
CONTIKI=../..
WITH_UIP6=1
UIP_CONF_IPV6=1
CFLAGS+= -DUIP_CONF_IPV6_RPL -DUIP_CONF_IPV6 -DWITH_UIP6
LDLIBS=-lm
ifdef PERIOD
CFLAGS=-DPERIOD=$(PERIOD)
endif
include $(CONTIKI)/Makefile.include
I have given execute permissions to the Makefile. After running make, the following message is displayed.
make: Nothing to be done for 'all'.
If CONTIKI_PROJECT should be assigned some value before all:, then what should it be?
I am not able to understand if I am missing anything from contiki point of view or it is just to do something with the Makefile.
How do I make this project work?
CONTIKI_PROJECT should refer to the name of your application, which is the same as the name of main .c file with the application's source code.
Here is the hello-world example Makefile from the project you linked to:
CONTIKI_PROJECT = hello-world
all: $(CONTIKI_PROJECT)
CONTIKI = ../..
include $(CONTIKI)/Makefile.include
I have problem with my makefile. I'm working on Eclipse in Windows and my file structure is like below (project path: D:/workspace):
Genesha
|
|___bin
| |_genesha
| |_main
| |_java
|___src |__Jni.class
|_genesha
|_main
|_jni
|__makefile
When I in cmd from localization of makefile (D:\workspace\Genesha\src\genesha\main\jni) I used command:
javah -o FileOperationsLibrary.h -jni -classpath ../../../../bin genesha.main.java.Jni
it works correctly. But when I used my makefile, I have following error:
make: *** No rule to make target `genesha.main.java.Jni.class', needed by `FileOperationsLibrary.h'. Stop.
I was searching long time error and now I have not idea what's wrong here...
EDIT: my makefile
FileOperationsLibrary.h: genesha.main.java.Jni.class
javah -o FileOperationsLibrary.h -jni -classpath ../../../../bin genesha.main.java.Jni
EDIT 2: Finally, thanks to MadScientist my make file code is:
FileOperationsLibrary.h: ../../../../bin/genesha/main/java/Jni.class
javah -o FileOperationsLibrary.h -jni -classpath ../../../../bin genesha.main.java.Jni
Thank you a lot for help :)
That error means that in your makefile somewhere you have a target FileOperationsLibrary.h that lists genesha.main.java.Jni.class as a prerequisite, something like:
FileOperationsLibrary.h: genesha.main.java.Jni.class
The file genesha.main.java.Jni.class does not exist, so make tries to find a way to build it. However there are no rules defined in the makefile that tell it how to build that file, so you get that error message.