I am having trouble with the following code.
CFG_PATH := cfg_path
include ${CFG_PATH}/makefile.cfg
INPUT_DIR=${PROG_INPUT_DIR}/input
MANIFEST_FILE = ${MANIFEST_DIR}/manifest.xml
$(shell mkdir -p ${INPUT_DIR})
Some_Target:
.
.
.
.
Target:
When I call this makefile from another makefile it is failing at the include line and I get the following error
ERROR: ${CFG_PATH}/makefile.cfg no such file or directory found.
In our current system, this code work fine as is and it executes fine but when I try to call it from another makefile it fails and I get that error
How I am calling the makefile.
${MAKE} Target -f ${makefile_location}/makefile
Thanks in advance!
Related
I am new to ubuntu and hence to make file. I have successfully created make file with folder structure. However, if I add the similar structure, I get an error.
I successfully executed make command and ran application with one main cpp file and two files (list_menu.cpp and list_menu.h ) in sub folder cpp11_and_cpp14_menu
folder structure looks exactly like below where cpp11_and_cpp14.cpp has the main function.
../advancedcppproject/
cpp11_and_cpp14.cpp
Makefile
../advancedcppproject/cpp11_and_cpp14_menu
list_menu.cpp
list_menu.h
../advancedcppproject/multi_threading_example
multi_threading.cpp
multi_threading.h
Make file contents are
cpp11_and_cpp14 : cpp11_and_cpp14.o ./multi_threading_example/multi_threading.o ./cpp11_and_cpp14_menu/list_menu.o
g++ cpp11_and_cpp14.o ./multi_threading_example/multi_threading.o ./cpp11_and_cpp14_menu/list_menu.o -o cpp11_and_cpp14
cpp11_and_cpp14.o : cpp11_and_cpp14.cpp ./cpp11_and_cpp14_menu/list_menu.h ./multi_threading_example/multi_threading.h
g++ -c cpp11_and_cpp14.cpp
./cpp11_and_cpp14_menu/list_menu.0 : ./cpp11_and_cpp14_menu/list_menu.cpp ./cpp11_and_cpp14_menu/list_menu.h
g++ -c ./cpp11_and_cpp14_menu/list_menu.cpp
./multi_threading_example/multi_threading.o : ./multi_threading_example/multi_threading.cpp ./multi_threading_example/multi_threading.h
g++ -c ./multi_threading_example/multi_threading.cpp
After executing make command, it fails with an error message
g++ -c ./multi_threading_example/multi_threading.cpp
g++ cpp11_and_cpp14.o ./multi_threading_example/multi_threading.o ./cpp11_and_cpp14_menu/list_menu.o -o cpp11_and_cpp14
g++: error: ./multi_threading_example/multi_threading.o: No such file or directory
Makefile:6: recipe for target 'cpp11_and_cpp14' failed
make: *** [cpp11_and_cpp14] Error 1
I expect multi_threading.o to be created under folder ../advancedcppproject/multi_threading_example. However multi_threading.o is created under ../advancedcppproject.
Where as list_menu.o is correctly created under ../advancedcppproject/cpp11_and_cpp14_menu.
What is wrong?
I am following this tutorial and I have gotten to the point where I need to 'make' compiled image to get it into pi, but I am getting following error:
mkdir build/
The syntax of the command is incorrect.
Makefile:57: recipe for target 'build/' failed
mingw32-make: *** [build/] Error 1
The makefile is available here in the template. Lines 56 + 57 look like this:
$(BUILD):
mkdir $#
Can anyone tell me what's wrong and how to fix it? I am new to this and following the step by step guide :/ Thank you!
Thanks to igagis' coment I have discovered what the problem was that: mkdir build/ is incorrect command because of the slash sign '/'.
In the make file, the variable target is defined as: BUILD = build/ because it is later used as a path. I fixed line 57 as following:
$(BUILD):
mkdir build
and the code now compiles as intended.
I am trying to run https://github.com/pavanpongle/IoT-Wormhole-IDS. After following README.md and Instructions to run, I understood that I need to use the Makefile. I have properly indented the file which now looks as below:
DEFINES+=PROJECT_CONF_H=\"project-conf.h\"
all:$(CONTIKI_PROJECT)
CONTIKI=../..
WITH_UIP6=1
UIP_CONF_IPV6=1
CFLAGS+= -DUIP_CONF_IPV6_RPL -DUIP_CONF_IPV6 -DWITH_UIP6
LDLIBS=-lm
ifdef PERIOD
CFLAGS=-DPERIOD=$(PERIOD)
endif
include $(CONTIKI)/Makefile.include
I have given execute permissions to the Makefile. After running make, the following message is displayed.
make: Nothing to be done for 'all'.
If CONTIKI_PROJECT should be assigned some value before all:, then what should it be?
I am not able to understand if I am missing anything from contiki point of view or it is just to do something with the Makefile.
How do I make this project work?
CONTIKI_PROJECT should refer to the name of your application, which is the same as the name of main .c file with the application's source code.
Here is the hello-world example Makefile from the project you linked to:
CONTIKI_PROJECT = hello-world
all: $(CONTIKI_PROJECT)
CONTIKI = ../..
include $(CONTIKI)/Makefile.include
I have a configure script that generates a config.inc file containing some variable definitions and a makefile that imports those configurations using
include config.inc
The thing that bothers me is that if the user tries to run the makefile directly without first running configure they get an unhelpful error message:
makefile:2: config.inc: No such file or directory
make: *** No rule to make target 'config.inc'. Stop.
Is there a way for me to produce a better error message, instructing the user to first run the configure script, without resorting to the autoconf strategy of generating the full makefile from inside configure?
Sure, no problem; just do something like this:
atarget:
echo here is a target
ifeq ($(wildcard config.inc),)
$(error Please run configure first!)
endif
another:
echo here is another target
include config.inc
final:
echo here is a final target
Note this is definitely specific to GNU make; there's no portable way to do this.
EDIT: the above example will work fine. If the file config.inc exists, then it will be included. If the file config.inc does not exist, then make will exit as it reads the makefile (as a result of the error function) and never get to the include line so there will be no obscure error about missing include files. That's what the original poster asked for.
EDIT2: Here's an example run:
$ cat Makefile
all:
#echo hello world
ifeq ($(wildcard config.inc),)
$(error Please run configure first!)
endif
include config.inc
$ touch config.inc
$ make
hello world
$ rm config.inc
$ make
Makefile:5: *** Please run configure first!. Stop.
I gave up and decided to use autoconf and automake to handle my makefile-generation needs.
I'm using make to write a pipeline for biological data analysis. My project directory is:
PROJECT
- DATA
- SAMPLEA
- A1.FASTQ A2.FASTQ
- SAMPLEB
- B1.FASTQ B2.FASTQ
- RESULTS
- SRC
- makefile
My current makefile uses a wildcard to list the directory of all .FASTQ files in the DATA directory. Using pattern rules each .FASTQ file then goes through a series of recipes with the final output file written to the RESULTS directory. Instead, I would like to create a directory for each SAMPLE where the final output file is written:
PROJECT/RESULTS/SAMPLEA/A1.out
PROJECT/RESULTS/SAMPLEA/A2.out
PROJECT/RESULTS/SAMPLEB/B1.out
PROJECT/RESULTS/SAMPLEB/B2.out
I can do this by having the first recipe make the directory, however this throws an error when the second of the FASTQ files from the same SAMPLE also tries to create the directory. A few posts on stack overflow suggest using the -p flag on mkdir to ignore errors, however this apparently causes problems when I run the makefile in parallel using the -j flag. I thought about forcing a shell script at the start of the makefile to run, to check if the results directories are present, and if not then it should create them, but I'd like to try and solve this issue using just make.
Create directory before executing rule.
DATADIR := $(shell cd DATA; find * -type d)
create_results_dir:= $(shell for i in $(DATADIR); \
do test -d DATA/$$i && mkdir -p RESULTS/$$i; \
done)
all:
#echo do something.