I just made this test driver using AOSP kernel "https://android.googlesource.com/kernel/common"
I put my driver code "tdrive", under "common/drivers", in which contains 2 files "Makefile" and "hello_kernel.c"
I also added my module in the common/drivers/Makefile as obj-y
After I type "./build/build.sh"
I got build error as
make: *** [/work/android/aosp/repo-db845c/common/Makefile:185: __sub-make] Error 2
Nothing else for the error, I have no clue but open the makefile mentioned above, at the line 185 it looks like:
183 # Invoke a second make in the output directory, passing relevant variables
184 __sub-make:
185 $(Q)$(MAKE) -C $(abs_objtree) -f $(abs_srctree)/Makefile $(MAKECMDGOALS)
Anyone can tell where should I go to find my errors? Thanks!
PS - I also tried with
./build/build.sh -d
Related
I always get this error when I try to run my tests with coverage flags and type gcov <source-file>. This error only happens to the actual source files that the tests call functions from. When I run gcovr -r . it shows 100% coverage for the tests but 0% for the source files even though I know the functions where called because all tests pass. I have done some digging and it seems that this error happens when some functions are not compiled in sync if that makes sense. That one version is older than another. But how can I fix this? This is the command I run to compile the tests:
${CC} ${CFLAGS} --coverage -o ./tests/bin/compiled_tests -D TEST ${TEST_SOURCES} ${SOURCES} \
-I /usr/local/Cellar/criterion/2.3.3/include/ -L/usr/local/Cellar/criterion/2.3.3/lib -lcriterion.3.1.0
The error:
➜ gcov tests/bin/compiled_tests-main.gcno
writeSessionCommandsToGlobalHistoryFile: GCOV_TAG_COUNTER_ARCS mismatch, got 4294967266, expected 30
Invalid .gcda File!
File 'src/main.c'
Lines executed:0.00% of 313
Creating 'main.c.gcov'
mkdir .build && \
cd .build && \
./../configure --prefix=$HOME/my_octave && \ [1]
make -j2 && \ [2]
make check && \
make install
While running make -j2 I get the error as
error: print: error opening file 'extended.tex'
error: called from print>latex_standalone at line 1029 column 5
__opengl_print__ at line 214 column 5
print at line 759 column 16 plotimages at line 109 column 7
GEN doc/interpreter/gplot.pdfMakefile:27911: recipe for target `'doc/interpreter/extended.pdf' failedmake[2]: *** [doc/interpreter/extended.pdf] Error `1make[2]: *** Waiting for unfinished jobs....make[2]: Leaving directory `'/home/bhanu/octave/.build'Makefile:26305: recipe for target 'all-recursive' failedmake[1]: *** `[all-recursive] Error 1make[1]: Leaving directory '/home/bhanu/octave/.build'Makefile:9916:
recipe for target 'all' failedmake: *** [all] Error 2
Can someone help me solve the error? I am running it on Ubuntu 18.04 system.
Some times the build process tries to rebuild all the documentation.
I am building from the source octave-5.2.0.tar.lz file and
the usual workaround is just
touch AUTHORS BUGS INSTALL.OCTAVE
between configure and the first make in the
build tree.
At the end of build phase I have only two PDFs
./doc/interpreter/octave.pdf
./doc/liboctave/liboctave.pdf
Create file named 'extended.tex' like this:
touch doc/interpreter/extended.tex
You have to do this inside the octave/.build/ directory.
Do this for any errors similar to this in the future. It worked for me this way.
I am following this tutorial and I have gotten to the point where I need to 'make' compiled image to get it into pi, but I am getting following error:
mkdir build/
The syntax of the command is incorrect.
Makefile:57: recipe for target 'build/' failed
mingw32-make: *** [build/] Error 1
The makefile is available here in the template. Lines 56 + 57 look like this:
$(BUILD):
mkdir $#
Can anyone tell me what's wrong and how to fix it? I am new to this and following the step by step guide :/ Thank you!
Thanks to igagis' coment I have discovered what the problem was that: mkdir build/ is incorrect command because of the slash sign '/'.
In the make file, the variable target is defined as: BUILD = build/ because it is later used as a path. I fixed line 57 as following:
$(BUILD):
mkdir build
and the code now compiles as intended.
I have problem with my makefile. I'm working on Eclipse in Windows and my file structure is like below (project path: D:/workspace):
Genesha
|
|___bin
| |_genesha
| |_main
| |_java
|___src |__Jni.class
|_genesha
|_main
|_jni
|__makefile
When I in cmd from localization of makefile (D:\workspace\Genesha\src\genesha\main\jni) I used command:
javah -o FileOperationsLibrary.h -jni -classpath ../../../../bin genesha.main.java.Jni
it works correctly. But when I used my makefile, I have following error:
make: *** No rule to make target `genesha.main.java.Jni.class', needed by `FileOperationsLibrary.h'. Stop.
I was searching long time error and now I have not idea what's wrong here...
EDIT: my makefile
FileOperationsLibrary.h: genesha.main.java.Jni.class
javah -o FileOperationsLibrary.h -jni -classpath ../../../../bin genesha.main.java.Jni
EDIT 2: Finally, thanks to MadScientist my make file code is:
FileOperationsLibrary.h: ../../../../bin/genesha/main/java/Jni.class
javah -o FileOperationsLibrary.h -jni -classpath ../../../../bin genesha.main.java.Jni
Thank you a lot for help :)
That error means that in your makefile somewhere you have a target FileOperationsLibrary.h that lists genesha.main.java.Jni.class as a prerequisite, something like:
FileOperationsLibrary.h: genesha.main.java.Jni.class
The file genesha.main.java.Jni.class does not exist, so make tries to find a way to build it. However there are no rules defined in the makefile that tell it how to build that file, so you get that error message.
Is it possible to treat warnings as errors in a Makfile (and thus exit before Makefile proceeds)
Furthermore, is it possible to filter out which warning yields an error?
My use case: I want to use --warn-undefined-variables in combination with this so that Makefile will exit when a variable is undefined, which is a very common source of error. Obviously I don't want to manually check for each variable as this is error-prone/tedious. I couldn't find anything on this, but it's a pretty important/basic feature.
Note: I'm not looking for -Werror which is a gcc specific command not applicable to my use case.
If you're prepared to add a dependency to every target, you can make warnings into errors.
Here is a make file with an error in it ("SRCS" instead of "SRC"):
# Turn on the warning we want
MAKEFLAGS += --warn-undefined-variables
# Make sure MAKECMDGOALS is defined, so it doesn't cause an error itself
ifndef MAKECMDGOALS
MAKECMDGOALS = all
endif
SRC=hello.c
all: compile
# Fails if the Makefile contains any warnings.
# Run this Makefile with the same goals, but with the -n flag.
# Grep for warnings, and fail if any are found.
no-make-warnings:
! make -n $(MAKECMDGOALS) 2>&1 >/dev/null | grep warning
# Targets you want to check must depend on no-make-warnings
compile: no-make-warnings
gcc -o hello $(SRCS)
When I run it, I see this:
$ make
! make -n all 2>&1 >/dev/null | grep warning
Makefile:17: warning: undefined variable `SRCS'
make: *** [no-make-warnings] Error 1
You just need to make every target that you want to be checked depend on the target no-make-warnings.
If someone knows how to do that automatically, please chime in.
The standard version of make does not support what you are looking for. However, it should not be difficult to build your own version of make to fulfill your use case.
Looking at the source code of make 3.82, check out the macro warn_undefined in variable.h:
214 /* Warn that NAME is an undefined variable. */
215
216 #define warn_undefined(n,l) do{\
217 if (warn_undefined_variables_flag) \
218 error (reading_file, \
219 _("warning: undefined variable `%.*s'"), \
220 (int)(l), (n)); \
221 }while(0)
I have not tried this, but I think it should be sufficient to replace error with fatal.