VHDL Shift Register not rotating right - vhdl

Question

Can someone help me figure out why my shift register won't rotate right. I know its not the switch inputs because I switched sw(14) with sw(15) and it still rotated left but not right. I think it is something in the actual coding but I'm not sure what.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity question2 is
Port (
led: buffer std_logic_vector (9 downto 0);
clk: in std_logic;
btnU: in std_logic;
btnD: in std_logic;
btnC: in std_logic;
sw: in std_logic_vector (15 downto 14)--------rotate prob. is not in switches
);
end question2;
architecture Behavioral of question2 is
constant active: std_logic :='1';
signal DataIn: std_logic_vector (9 downto 0):= "0000000001";
signal Load: std_logic := btnD;
signal Reset: std_logic := btnC;
signal Left: std_logic:= sw(15);
signal Right: std_logic:= sw(14);
signal DataOut: std_logic_vector (9 downto 0);
signal Clear: std_logic:= btnU;
signal speed_enable: std_logic;
begin
led<= DataOut;
SpeedControl: process (clk, Reset)
variable counter: integer range 0 to 10000000;
begin
speed_enable<=not active;
if Reset = Active then
counter:= 0;
elsif (rising_edge (clk)) then
counter := counter + 1;
if (counter=10000000) then
speed_enable<= Active;
counter:=0;
end if;
end if;
end process;
shiftregister: process(clk, clear)
begin
if rising_edge (clk) then
if clear= active or reset=active then
DataOut <= (others => '0');
elsif load = active then
DataOut <= DataIn ;
elsif Left = active and Right = not active then
if speed_enable = active then
DataOut <= DataOut(8 downto 0) & DataOut(9) ;
elsif Right = active and left = not active then
if speed_enable = active then
DataOut <= DataOut(0) & DataOut (9 downto 1) ;
else
dataout <= "0000000000";
end if;
end if;
end if;
end if;
end process;
end Behavioral;

Answer 1

You haven't fixed all the problems I mentioned on your last question. Default assignments are not default connections; your Left and Right signals won't change when your sw input changes.
You should connect the internal control signals to your inputs right below the led<= DataOut; line with something like Left <= sw(15);
Furthermore, when no control signals are active dataout should be unchanged, not reset itself to all '0's. Your load, reset, and clear buttons aren't going to work either. speed_enable is still mixing combinational assignments and clocked assignments and won't synthesize.
DataIn might as well be a constant since there is no way to modify it.
It also looks like you're missing the end if; for the clock enables (you stick them at the end instead of where they should be) which will cause undesired behavior.