VHDL 10 bit Shift Register - vhdl

Question

I am trying to create a 10 bit shift register. However I keep getting the error
[DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 2 out of 15 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk, btnu.
everytime I got to write the bit stream. Can someone help point me in the right direction and point out any other mistakes I am making that will not allow my shift register to function properly.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity question2 is
Port (
led: out std_logic_vector (9 downto 0);
Clk: in std_logic;
btnu: in std_logic;
btnL: in std_logic;
btnR: in std_logic ;
btnD: in std_logic;
btnC: in std_logic
);
end question2;
architecture Behavioral of question2 is
constant active: std_logic :='1';
constant inactive: std_logic :='0';
constant step_zero: std_logic_vector(9 downto 0) :="0000000000";
constant step_one: std_logic_vector(9 downto 0) :="0000000001";
constant step_two: std_logic_vector(9 downto 0) :="0000000010";
constant step_three: std_logic_vector(9 downto 0) :="0000000100";
constant step_four: std_logic_vector(9 downto 0) :="0000001000";
constant step_five: std_logic_vector(9 downto 0) :="0000010000";
constant step_six: std_logic_vector(9 downto 0) :="0000100000";
constant step_seven: std_logic_vector(9 downto 0) :="0001000000";
constant step_eight: std_logic_vector(9 downto 0) :="0010000000";
constant step_nine: std_logic_vector(9 downto 0) :="0100000000";
constant step_ten: std_logic_vector(9 downto 0) :="0100000000";
signal DataIn: std_logic_vector (9 downto 0):= "0000000001";
signal Load: std_logic := btnD;
signal Reset: std_logic;
signal Left: std_logic:= btnL;
signal Right: std_logic:= btnR;
signal DataOut: std_logic_vector (9 downto 0);
signal Clear: std_logic:= btnU;
signal speed_enable: std_logic;
begin
SpeedControl: process (clk)
variable counter: integer range 0 to 10000000;
begin
speed_enable<=not active;
if Reset = Active then
counter:= 0;
elsif (rising_edge (clk)) then
counter := counter + 1;
if (counter=10000000) then
speed_enable<= Active;
counter:=0;
end if;
end if;
end process;
shiftregister: process(speed_enable, clear, DataIn)
begin
if speed_enable=active then
if clear=active then
DataOut (9 downto 0) <= "0000000000"; --(others=>'0');
elsif load = Active then
DataOut (9 downto 0) <= DataIn ;
elsif Left = Active then
DataOut (9 downto 0) <= DataOut(7 downto 0) & "11" ;
elsif Right = Active then
DataOut (9 downto 0) <= DataOut (9 downto 2) & "11" ;
end if;
end if;
end process;
LEDSTEP: process(DataOut)
begin
if DataOut = "0000000000" then
led <= step_zero;
elsif DataOut = "0000000001" then
led <= step_one;
elsif DataOut = "0000000010" then
led <= step_two;
elsif DataOut = "0000000100" then
led <= step_three;
elsif DataOut = "000001000" then
led <= step_four;
elsif DataOut = "0000010000" then
led <= step_five;
elsif DataOut = "0000100000" then
led <= step_six;
elsif DataOut = "0001000000" then
led <= step_seven;
elsif DataOut = "0010000000" then
led <= step_eight;
elsif DataOut = "0100000000" then
led <= step_nine;
elsif DataOut = "1000000000" then
led <= step_ten;
end if;
end process;
end Behavioral;

Answer 1

As stated in the comments, this is an issue with your design constraints. A detailed description of (and typical solutions to) the problem are outlined in the Xilinx support answers.
However, in this specific instance, you have actually specified the PACKAGE_PIN and IOSTANDARD constraints for the ports that are being complained about (clk and btnU). The issue is actually due to the difference in case between your vhd file and the xdc file (which, due to being Tcl, is case sensitive). In your vhd file, the ports that cause the errors are Clk and btnu - These do not exist in the constraints file.
To resolve this, modify your port declaration to be:
entity question2 is
Port (
led: out std_logic_vector (9 downto 0);
clk: in std_logic;
btnU: in std_logic;
btnL: in std_logic;
btnR: in std_logic ;
btnD: in std_logic;
btnC: in std_logic
);
end question2;
(Conversely, you could modify the constraints file, but you would be altering the naming conventions used).
A similar issue discussing case sensitivites in constraint files is described here.