Using of loop statements and delays inside the states in fsm - vhdl

Question

I'm trying to write vhdl code for a spartan-6 xc6slx45t for generating multiple frequencies in single channel.. That is:
242.72khz with 20 cycles
23.6khz with 1 cycle
243.90khz with 6 cycles
then 23.4 khz with 386 cycles
all in single output. I just tried with one frequency here and got some issues with delays in codes..
I mentioned each states with different no.of cycles here.. But what I need is for example: when state S0 =>242.72khz with 20 cycles and then a delay in between two states, and next state S1 => 23.6khz with one cycle and then again a delay and next state and so on..)
Here i attached my code. Please help me with developing the code..
Thanks in advance...
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FSM_Example IS
PORT (
clk, reset, en : IN std_logic;
output : INOUT std_logic
);
END FSM_Example;
ARCHITECTURE Behavioral OF FSM_Example IS
TYPE state_type IS (S0, S1, S2, S3);
SIGNAL cur_state, next_state : state_type;
SIGNAL count : INTEGER RANGE 0 TO 5000;
SIGNAL i : INTEGER RANGE 0 TO 400;
SIGNAL cnt : INTEGER RANGE 0 TO 400;
BEGIN
state_memory : PROCESS (clk, reset)
BEGIN
IF (reset = '1') THEN
cur_state <= S0;
ELSIF (clk = '1' AND clk'event) THEN
IF (count = 4240 - 1) THEN
count <= 0;
cur_state <= next_state;
ELSE
count <= count + 1;
END IF;
END IF;
END PROCESS state_memory;
PROCESS (count)
BEGIN
IF (count < 1480) THEN
output <= '1';
ELSE
output <= '0';
END IF;
END PROCESS count;
PROCESS (en, cur_state)
BEGIN
CASE cur_state IS
WHEN S0 =>
loop0 : FOR i IN 0 TO 6 LOOP
EXIT loop0 WHEN i = 7;
cnt(i + 1) <= cnt(i) + 1;
IF (en = '1' AND en'event) THEN
ELSIF (i < 6) THEN
next_state <= S1;
ELSE
next_state <= S0;
END IF;
END LOOP;
WHEN S1 =>
loop1 : FOR i IN 0 TO 1 LOOP
EXIT loop1 WHEN i = 2;
i <= i + 1;
IF (en = '1' AND en'event) THEN
ELSIF (i < 1) THEN
next_state <= S2;
ELSE
next_state <= S1;
END IF;
END LOOP;
WHEN S2 =>
loop2 : FOR i IN 0 TO 20 LOOP
EXIT loop2 WHEN i = 21;
i <= i + 1;
IF (en = '1' AND en'event) THEN
ELSIF (i < 20) THEN
next_state <= S3;
ELSE
next_state <= S2;
END IF;
END LOOP;
WHEN S3 =>
loop3 : FOR i IN 0 TO 386 LOOP
EXIT loop3 WHEN i = 387;
i <= i + 1;
IF (en = '1' AND en'event) THEN
ELSIF (i < 386) THEN
next_state <= S0;
ELSE
next_state <= S3;
END IF;
END LOOP;
END CASE;
END PROCESS;
END Behavioral;

Answer 1

You are trying to write synthesize code. Then you cannot use wait for x ns. The FPGA does not know how to wait for x nanoseconds. It does not know what a nanosecond is.
But more of your code does not seem synthesizable. You should read-up on how to write VHDL for synthesis on FPGAs
What an FPGA does have (normally) is a clock crystal input and also . From the frequency of the clock input, you can derive how many clock cycles would be in a time period. Then you should implement a counter and insert intermediate wait-states, where the fsm waits until a specific value of the counter is reached.
E.g. If the clock input is 100 MHz, each clock pulse is 10 ns long ==> 10 clock pulses is 100 ns long. If you need smaller time step, you need to increase the clock frequency using a PLL/DCM/MMCM/etc. but you cannot do this indefinitely, as the FPGA does not support very high clock frequencies.