Please understand my very low skill-set on the code. I am trying to learn to be better.
Using DE0 Nano board, I am trying to write VHDL to simulate all available LEDs on the board (8 of them)
I labeled them LED0 ~ LED7. Using 50 MHZ and 1/2 s counter, I wanted to operate individual LEDs in order.
For example, if these individual bits represents on and off of the LEDs.
1|0|0|0|0|0|0|0 -> 0|1|0|0|0|0|0|0 -> 0|0|1|0|0|0|0|0 and so on. At the end, counter would reset back to 0 to repeat the sequence again.
Please view my code below with these questions/issues.
1) I get one 1/2 s pause after 8th LED. Why? How do I fix this?
2) Even if i put the variable counter as 8, it repeats as 16 thus I had to implement the reset of the counter to 0. (marked as question 2 in the code)
3) Is there any better way to write these codes? It is completely messy. Could you give tips on any other function or method I can use to shorten this codes?
Please let me know if any questions!
THANKS A LOT FOR THE HELP.
entity ledtest is
port(
clk_50mhz : in std_logic ;
reset_btn : in std_logic;
green_led : out std_logic_vector(7 downto 0)
);
end entity;
architecture behave of ledtest is
signal clk_1hz : std_logic ;
signal scaler : integer range 0 to 25000000 ;
signal counter : integer range 0 to 8;
signal LED : std_logic_vector(7 downto 0);
begin
clk_1hz_process : process( clk_50mhz , reset_btn )
begin
if (reset_btn = '0') then
clk_1hz <= '0';
scaler <= 0;
counter <= 0;
elsif(rising_edge(clk_50mhz)) then
if (scaler < 25000000) then
scaler <= scaler + 1 ;
clk_1hz <= '0';
else
scaler <= 0;
clk_1hz <= '1';
counter <= counter + 1;
if (counter >= 8) then --------question 2
counter <= 0;
end if;
end if;
end if;
end process clk_1hz_process;
blinking_process : process (clk_1hz,reset_btn)
begin
if (reset_btn = '0') then
LED(0) <= '0';
elsif rising_edge(clk_1hz) AND counter = 1 then
LED(0) <= not LED(0) ;
LED(7) <= '0' ;
elsif rising_edge(clk_1hz) AND counter = 2 then
LED(1) <= not LED(1) ;
LED(0) <= not LED(0) ;
elsif rising_edge(clk_1hz) AND counter = 3 then
LED(2) <= not LED(2) ;
LED(1) <= not LED(1) ;
elsif rising_edge(clk_1hz) AND counter = 4 then
LED(3) <= not LED(3) ;
LED(2) <= not LED(2) ;
elsif rising_edge(clk_1hz) AND counter = 5 then
LED(4) <= not LED(4) ;
LED(3) <= not LED(3) ;
elsif rising_edge(clk_1hz) AND counter = 6 then
LED(5) <= not LED(5) ;
LED(4) <= not LED(4) ;
elsif rising_edge(clk_1hz) AND counter = 7 then
LED(6) <= not LED(6) ;
LED(5) <= not LED(5) ;
elsif rising_edge(clk_1hz) AND counter = 8 then
LED(7) <= not LED(7) ;
LED(6) <= not LED(6) ;
end if;
end process blinking_process;
green_led(0) <= LED(0);
green_led(1) <= LED(1);
green_led(2) <= LED(2);
green_led(3) <= LED(3);
green_led(4) <= LED(4);
green_led(5) <= LED(5);
green_led(6) <= LED(6);
green_led(7) <= LED(7);
end behave;
If your readers squint real hard they can treat the original post as one question and two issues. (A questions is singular.)
Please view my code below with these questions/issues.
1) I get one 1/2 s pause after 8th LED. Why? How do I fix this?
There are 9 counter values (0 to 8) and only 8 LEDs (7 downto 0). No assignments occur in the half second between assigning counter to 0 and incrementing by 1 again.
2) Even if i put the variable counter as 8, it repeats as 16 thus I had to implement the reset of the counter to 0. (marked as question 2 in the code)
This issue is tied in with 1). The requirement for evaluating counter greater than or equal to 8 is caused by assigning counter to 8, again there are 9 values and only 8 LEDs. Note that's a synchronous load to 0 and not an asynchronous reset.
3) Is there any better way to write these codes? It is completely messy. Could you give tips on any other function or method I can use to shorten this codes?
Because you're attempting to go directly to FPGA instead of simulating the focus on tips should relate to the question 1) and how to fix it. There are also some synthesis issues, here gating clocks by adding enables to the conditions in if statement elsif alternatives. There's also the issue of design specification complexity and the amount of debugging effort associated with the number of lines of code.
First there are flip flops for all LED elements as well a counter. We can reduce the number of flip flops to one for each LED element by using a ring counter (not to be confused with a Johnson counter).
Assignments to green_led (the std_logic_vector) can be from LED (the std_logic_vector) instead of element by element. There's a one to one correspondence between element indices on both side of the assignment(s).
Also to allow simulation you could virtualize the time interval of a half second loaded into scalar. This has the effect of having fewer clocks represent a half second. The idea is simulation doesn't have to take the 10+ seconds of 100 million clock transitions per second (rising and falling edges).
Throw all these together and the code is changed to look like:
library ieee;
use ieee.std_logic_1164.all;
entity ledtest is
generic (half_second: integer := 24999999); -- zero identity
-- the generic allows fewer clocks per second for simulation
port (
clk_50mhz: in std_logic;
reset_btn: in std_logic;
green_led: out std_logic_vector(7 downto 0)
);
end entity;
architecture behave of ledtest is
signal clk_1hz: std_logic;
signal scaler: integer range 0 to half_second;
-- signal counter: integer range 0 to 8; -- DELETED
signal ring_counter: std_logic_vector (7 downto 0); -- ADDED
signal LED: std_logic_vector (7 downto 0);
signal LED0I: std_logic; -- ADDED
begin
LED0I <= '1' when LED = "00000000" else
'0';
clk_1hz_process:
process (clk_50mhz, reset_btn)
begin
if reset_btn = '0' then
clk_1hz <= '0';
scaler <= 0;
-- counter <= 0;
elsif rising_edge(clk_50mhz) then
if scaler /= half_second then
scaler <= scaler + 1;
clk_1hz <= '0';
else
scaler <= 0;
clk_1hz <= '1';
-- counter <= counter + 1;
-- if counter >= 8 then --------question 2
-- counter <= 0;
-- end if;
end if;
end if;
end process clk_1hz_process;
blinking_process:
process (clk_1hz, reset_btn)
begin
if reset_btn = '0' then
LED <= (others => '0');
-- LED(0) <= '0';
elsif rising_edge(clk_1hz) then
LED <= LED(6 downto 0) & (LED(7) or LED0I);
-- ring counter with a roulette ball lauch after reset
-- elsif rising_edge(clk_1hz) AND counter = 1 then
-- LED(0) <= not LED(0);
-- LED(7) <= '0';
-- elsif rising_edge(clk_1hz) AND counter = 2 then
-- LED(1) <= not LED(1);
-- LED(0) <= not LED(0);
-- elsif rising_edge(clk_1hz) AND counter = 3 then
-- LED(2) <= not LED(2);
-- LED(1) <= not LED(1);
-- elsif rising_edge(clk_1hz) AND counter = 4 then
-- LED(3) <= not LED(3);
-- LED(2) <= not LED(2);
-- elsif rising_edge(clk_1hz) AND counter = 5 then
-- LED(4) <= not LED(4);
-- LED(3) <= not LED(3);
-- elsif rising_edge(clk_1hz) AND counter = 6 then
-- LED(5) <= not LED(5);
-- LED(4) <= not LED(4);
-- elsif rising_edge(clk_1hz) AND counter = 7 then
-- LED(6) <= not LED(6);
-- LED(5) <= not LED(5);
-- elsif rising_edge(clk_1hz) AND counter = 8 then
-- LED(7) <= not LED(7);
-- LED(6) <= not LED(6);
end if;
end process blinking_process;
green_led <= led;
-- green_led(0) <= LED(0);
-- green_led(1) <= LED(1);
-- green_led(2) <= LED(2);
-- green_led(3) <= LED(3);
-- green_led(4) <= LED(4);
-- green_led(5) <= LED(5);
-- green_led(6) <= LED(6);
-- green_led(7) <= LED(7);
end architecture behave;
(Also note the default generic value scalar is reset and loaded to has been decremented to include the unity 0 in the 250,000,000 clocks be half second. The equality test for half_second is simpler than using magnitude comparison.)
Using a ring counter reduces complexity and side steps the issue of a counter range of 9.
The ring counter has a flourish added, the reset value is all '0's which are detected by signal LED0I which is used to start the ring counter after reset. It prevents all the LEDs from being lit during reset.
You can use a testbench with the number of clocks comprising a half second to a much smaller number allowing fast simulation with small waveform dump files:
library ieee;
use ieee.std_logic_1164.all;
entity ledtest_tb is
end entity;
architecture foo of ledtest_tb is
signal clk: std_logic := '0';
signal reset_btn: std_logic := '1';
signal green_led: std_logic_vector (7 downto 0);
begin
DUT:
entity work.ledtest
generic map (half_second => 7)
port map (
clk_50mhz => clk,
reset_btn => reset_btn,
green_led => green_led
);
CLOCK:
process
begin
wait for 0.5 sec / 7;
clk <= not clk;
if now > 19 sec then
wait;
end if;
end process;
STIMULUS:
process
begin
wait for 0.5 sec;
reset_btn <= '0';
wait for 0.5 sec;
reset_btn <= '1';
wait;
end process;
end architecture;
And that gives:
You could eliminate the generic map in the testbench instantiation of ledtest to demonstrate the difference in simulation time and dump file size inherent with simulating every clock transition with a 50 MHz clock. The idea here is it's easier to troubleshoot a simulation than it is to guess from what you can see (here the LEDs). Because the code description was simplified there was debugging required using the original code as a starting point. It did rely on a knowledge of digital electronics and VHDL.
The simulation was done with ghdl and gtkwave.
Related
I am trying to make a basic distance indicating module using ultrasonic sensor. When I dumped the code for the same into my FPGA board(Helium V1.1 developed by IIT-B) all the LEDs in the board started glowing since the clock frequency was too high. So now I am using a frequency divider to reduce my clock speed but I am not getting how to use the output of my frequency divider code as an input to my main code. Can someone help me since this is the first time I am working on FPGA and I dont quite understand VHDL yet?
Code for frequency divider
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity Clock_Divider is
port ( clk,reset: in std_logic;
clock_out: out std_logic);
end Clock_Divider;
architecture bhv of Clock_Divider is
signal count: integer:=1;
signal tmp : std_logic := '0';
begin
process(clk,reset)
begin
if(reset='1') then
count<=1;
tmp<='0';
elsif(clk'event and clk='1') then
count <=count+1;
if (count = 25000) then
tmp <= NOT tmp;
count <= 1;
end if;
end if;
clock_out <= tmp;
end process;
end bhv;
Code to measure distance using ultrasonic:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ultrasonic is
port(
CLOCK: in std_logic;
LED: out std_logic_vector(7 downto 0);
TRIG: out std_logic;
ECHO: in std_logic
);
end ultrasonic;
architecture rtl of ultrasonic is
signal microseconds: std_logic;
signal counter: std_logic_vector(17 downto 0);
signal leds: std_logic_vector(7 downto 0);
signal trigger: std_logic;
begin
process(CLOCK)
variable count0: integer range 0 to 7;
begin
if rising_edge(CLOCK) then
if count0 = 5 then
count0 := 0;
else
count0 := count0 + 1;
end if;
if count0 = 0 then
microseconds <= not microseconds;
end if;
end if;
end process;
process(microseconds)
variable count1: integer range 0 to 262143;
begin
if rising_edge(microseconds) then
if count1 = 0 then
counter <= "000000000000000000";
trigger <= '1';
elsif count1 = 10 then
trigger <= '0';
end if;
if ECHO = '1' then
counter <= counter + 1;
end if;
if count1 = 249999 then
count1 := 0;
else
count1 := count1 + 1;
end if;
end if;
end process;
process(ECHO)
begin
if falling_edge(ECHO) then
if counter < 291 then
leds <= "11111111";
elsif counter < 581 then
leds <= "11111110";
elsif counter < 871 then
leds <= "11111100";
elsif counter < 1161 then
leds <= "11111000";
elsif counter < 1451 then
leds <= "11110000";
elsif counter < 1741 then
leds <= "11100000";
elsif counter < 2031 then
leds <= "11000000";
elsif counter < 2321 then
leds <= "10000000";
else
leds <= "00000000";
end if;
end if;
end process;
LED <= leds;
TRIG <= trigger;
end rtl;
I am using Quartus for simulating these codes.
welcome to the HDL languages :)
For simulation clock_out is missing from the sensitivity list process(...)
For synthesis/implementation you might need to check all processes as they should be dependent on your clock signal. I've learned it's considered bad practice to use rising/falling edge on other signals than clock signals.
You probably want to go for a pattern something like:
...
-- entity declaration
s : in std_logic;
...
-- architecture declaration
signal s_d : std_logic;
begin
...
process(clk)
begin
if rising_edge(clk) then
-- s_d is s one clock cycle delayed
s_d <= s;
-- detect s transition from 0 to 1 == rising edge
if s = '1' and s_d = '0' then
-- Code dependent on rising edge s
end if;
end if;
end process;
NOTE: s may be an internal signal and is not needed to come from entity. If s is a strobe (1 clock cycle long generated with the same clock) s_d is not needed as there is no need to detect the edge, just the signal state.
I want to make a UART receiver that reads 8 consecutives bits with a parity bit at the end and with a simple stop bit. My FPGA have a clock of 100Mhz and the data that are transmitted to the uart have a rate of 56700 bauds. The dividing factor is 1736 (56700 * 1736 ≈ 100Mhz). The two outputs are the message of the input decoded by the uart and an error signal that indicates if the uart have correctly read the input. This is what I have :
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity uart_receiver is
generic (
clksPerBit : integer := 1736 -- Needs to be set correctly
);
port (
clk : in std_logic;
clk_en_uart : in std_logic ;
reset : in std_logic;
uart_rx : in std_logic;
error : out std_logic;
char : out std_logic_vector(7 downto 0)
);
end uart_receiver;
architecture uart_receiver_arch of uart_receiver is
type etat is (init, start_bit, receiving_bits, parity_bit,
stop_bit );
signal current_state : etat := init ;
signal error_signal : std_logic := '0';
signal clk_count : integer range 0 to clksPerBit-1 := 0;
signal bit_index : integer range 0 to 7 := 0; -- 8 Bits Total
signal data_byte : std_logic_vector(7 downto 0) := (others => '0');
begin
process (clk_en_uart)
begin
if rising_edge(clk_en_uart) then
end if;
end process;
process (clk,reset)
variable check_parity : integer range 0 to 7 := 0;
begin
if (reset = '1') then
current_state <= init;
error_signal <= '0';
clk_count <= 0;
bit_index <= 0;
data_byte <= (others => '0');
elsif rising_edge(clk) then
case current_state is
when init =>
clk_count <= 0;
Bit_Index <= 0;
if uart_rx = '0' then -- Start bit detected
current_state <= start_bit;
else
current_state <= init;
end if;
when start_bit =>
if clk_count = (clksPerBit-1)/2 then
if uart_rx = '0' then
clk_count <= 0; -- reset counter since we found the middle
current_state <= receiving_bits;
else
current_state <= init;
end if;
else
clk_count <= clk_count + 1;
current_state <= start_bit;
end if;
when receiving_bits =>
if clk_count < clksPerBit-1 then
clk_count <= clk_count + 1;
current_state <= receiving_bits;
else
clk_count <= 0;
data_byte(bit_index) <= uart_rx;
if bit_index < 7 then
bit_index <= bit_index + 1;
current_state <= receiving_bits ;
else
bit_index <= 0;
current_state <= parity_bit;
end if;
end if;
when parity_bit =>
if clk_count < clksPerBit-1 then
clk_count <= clk_count + 1;
current_state <= parity_bit;
else
for k in 0 to 7 loop
if ( data_byte(k) = '1' ) then
check_parity := check_parity + 1 ;
end if;
end loop;
if((uart_rx = '1' and check_parity mod 2 = 0) or (uart_rx = '0' and check_parity mod 2 = 1)) then
error_signal <= '1' ;
else
error_signal <= '0';
end if ;
current_state <= stop_bit;
end if;
when stop_bit =>
if clk_count < clksPerBit-1 then
clk_count <= clk_count + 1;
current_state <= stop_bit ;
else
clk_count <= 0;
current_state <= init;
end if;
when others =>
current_state <= init;
end case;
end if;
char <= data_byte ;
error <= error_signal ;
end process;
end uart_receiver_arch;
So there's a phase shift between the data that is transmitted to the uart and his clock. If there's a phase shift, I'm not reading the data at the right time. I think that this code is sufficient to solve this problem. But, I've created a clock_divider and I can't seem to find a way to use it in this code. This is my clock divider :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clock_divider is
generic (divfactor : positive := 1736);
Port (clk,clk2, reset : in STD_LOGIC ;
clkdiv, activationsig : out STD_LOGIC );
end clock_divider;
architecture clock_divider_arch of clock_divider is
begin
process(clk,reset)
variable clksigv : std_logic := '0' ;
variable activationsigv : std_logic := '0' ;
variable count : integer := 0 ;
begin
if (reset = '1') then
clksigv := '0' ;
activationsigv := '0' ;
count := 0 ;
elsif ( rising_edge(clk) ) then
count := count + 2 ;
if (activationsigv = '1') then
activationsigv := '0';
end if;
if ( count >= divfactor - 1 ) then
clksigv := not(clksigv) ;
if ( clksigv = '1' ) then
activationsigv := '1' ;
end if;
count := 0 ;
end if ;
end if ;
clkdiv <= clksigv ;
activationsig <= activationsigv;
end process ;
end clock_divider_arch;
The outputs of this clock divider are the clock divided and the activation signal that, when it is at '1', I have to read the data in the uart. So, the two outputs should also be inputs of the uart. In the uart_recevier, clk_en_uart is actually the clock divided, but I'm not using it because I don't know how.
I think that the solution is to 'activate' this divided clock when I enter in the start_bit case so that I have two clocks with the same phase and the same frequency, but I also think that it impossible to set a phase for a clock.
I'm not sure that I've clearly adressed my problem. If there's something that you don't understand in my code or in my explanation, feel free to ask questions.
Thank you for your help, hoping that I find a solution.
Sounds like the suggested solution is complicated for this problem.
A usual approach is that the receiver justs look for the falling edge of the start bit, then count for half a bit time (1736 / 2 cycles in your case), then samples the start bit value there, and subsequently samples the data, parity and stop bit values after each full bit time (1736 cycles in your case). After that start over looking for a new falling edge of the start bit.
The difference between the transmitter and receiver frequencies are then (usually) so small that the sample time will be practically in the middle for messages of only 11 bits at relative low bitrate, and the counter restart at falling edge of start bit ensures that any effect of long time frequency difference is removed.
I'm trying to write vhdl code for a spartan-6 xc6slx45t for generating multiple frequencies in single channel.. That is:
242.72khz with 20 cycles
23.6khz with 1 cycle
243.90khz with 6 cycles
then 23.4 khz with 386 cycles
all in single output. I just tried with one frequency here and got some issues with delays in codes..
I mentioned each states with different no.of cycles here.. But what I need is for example: when state S0 =>242.72khz with 20 cycles and then a delay in between two states, and next state S1 => 23.6khz with one cycle and then again a delay and next state and so on..)
Here i attached my code. Please help me with developing the code..
Thanks in advance...
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FSM_Example IS
PORT (
clk, reset, en : IN std_logic;
output : INOUT std_logic
);
END FSM_Example;
ARCHITECTURE Behavioral OF FSM_Example IS
TYPE state_type IS (S0, S1, S2, S3);
SIGNAL cur_state, next_state : state_type;
SIGNAL count : INTEGER RANGE 0 TO 5000;
SIGNAL i : INTEGER RANGE 0 TO 400;
SIGNAL cnt : INTEGER RANGE 0 TO 400;
BEGIN
state_memory : PROCESS (clk, reset)
BEGIN
IF (reset = '1') THEN
cur_state <= S0;
ELSIF (clk = '1' AND clk'event) THEN
IF (count = 4240 - 1) THEN
count <= 0;
cur_state <= next_state;
ELSE
count <= count + 1;
END IF;
END IF;
END PROCESS state_memory;
PROCESS (count)
BEGIN
IF (count < 1480) THEN
output <= '1';
ELSE
output <= '0';
END IF;
END PROCESS count;
PROCESS (en, cur_state)
BEGIN
CASE cur_state IS
WHEN S0 =>
loop0 : FOR i IN 0 TO 6 LOOP
EXIT loop0 WHEN i = 7;
cnt(i + 1) <= cnt(i) + 1;
IF (en = '1' AND en'event) THEN
ELSIF (i < 6) THEN
next_state <= S1;
ELSE
next_state <= S0;
END IF;
END LOOP;
WHEN S1 =>
loop1 : FOR i IN 0 TO 1 LOOP
EXIT loop1 WHEN i = 2;
i <= i + 1;
IF (en = '1' AND en'event) THEN
ELSIF (i < 1) THEN
next_state <= S2;
ELSE
next_state <= S1;
END IF;
END LOOP;
WHEN S2 =>
loop2 : FOR i IN 0 TO 20 LOOP
EXIT loop2 WHEN i = 21;
i <= i + 1;
IF (en = '1' AND en'event) THEN
ELSIF (i < 20) THEN
next_state <= S3;
ELSE
next_state <= S2;
END IF;
END LOOP;
WHEN S3 =>
loop3 : FOR i IN 0 TO 386 LOOP
EXIT loop3 WHEN i = 387;
i <= i + 1;
IF (en = '1' AND en'event) THEN
ELSIF (i < 386) THEN
next_state <= S0;
ELSE
next_state <= S3;
END IF;
END LOOP;
END CASE;
END PROCESS;
END Behavioral;
You are trying to write synthesize code. Then you cannot use wait for x ns. The FPGA does not know how to wait for x nanoseconds. It does not know what a nanosecond is.
But more of your code does not seem synthesizable. You should read-up on how to write VHDL for synthesis on FPGAs
What an FPGA does have (normally) is a clock crystal input and also . From the frequency of the clock input, you can derive how many clock cycles would be in a time period. Then you should implement a counter and insert intermediate wait-states, where the fsm waits until a specific value of the counter is reached.
E.g. If the clock input is 100 MHz, each clock pulse is 10 ns long ==> 10 clock pulses is 100 ns long. If you need smaller time step, you need to increase the clock frequency using a PLL/DCM/MMCM/etc. but you cannot do this indefinitely, as the FPGA does not support very high clock frequencies.
I have searched about this problem but it all seemed Greek to me so I came here as last effort.I have the following VHDL code that I want to be implemented on an fpga.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use work.conversions.all;
entity counter is
port ( clk_in: in std_logic; --new clock
target : in std_logic_vector(7 downto 1); --Set the target with the switches (SW7-SW1)
start : in std_logic; --Start/pause (SW0)
rst : in std_logic; --Reset (BT0)
LD : out std_logic_vector(7 downto 1); --Leds show the target at binary (LD7-LD1)
LD0 : out std_logic; --LD0 indicates thw the limit has been reached
seg : out std_logic_vector(7 downto 0); --7 segment display
digit : out std_logic_vector(3 downto 0)
);
end counter;
architecture Behavioral of counter is
begin
process(clk_in,target,rst)
variable timer : natural := 0;
variable counter : natural := 0;
variable display_counter : natural range 0 to 4 := 0;
begin
LD0 <= '0';
LD <= target; --Show the target at the leds
digit <= "1110"; --Last digit active
seg <= "00000011"; --Show zero
<--->if(rst='1') then --Reset counter
counter := 0;
timer := 0;
digit <= "1110"; --Last digit active
seg <= "00000011"; --Show zero
LD0 <= '0';
elsif rising_edge(clk_in) then
if(start = '0') then --Pause
--counter := counter;
elsif(counter = conv_integer(unsigned(target))) then --timer limit has been reached
LD0 <= '1';
else
counter := counter + 1;
display_counter := display_counter + 1;
if(counter rem 10 = 0) then --one second has elapsed (10Hz cycle)
timer := timer + 1; --increase timer
end if;
case display_counter is --Select which digits are gonna be activated and with what
when 1 =>
seg <= int2led(timer/1000);
if(int2led(timer/1000) = "00000000") then
digit(3) <= '1';
else
digit(3) <= '0';
end if;
when 2 =>
seg <= int2led((timer/100) mod 10);
if(int2led((timer/100) mod 10) = "00000000") then
digit(2) <= '1';
else
digit(2) <= '0';
end if;
when 3 =>
seg <= int2led((timer/10) mod 10);
if(int2led((timer/10) mod 10) = "00000000") then
digit(1) <= '1';
else
digit(1) <= '0';
end if;
when others =>
seg <= int2led(timer/10);
if(int2led(timer/10) = "00000000") then
digit(1) <= '1';
else
digit(1) <= '0';
end if;
end case;
if (display_counter = 4) then --reset the display counter from time to time
display_counter := 0;
else
display_counter := display_counter;
end if;
end if;
end if;
end process;
end Behavioral;
The problem is at if(rst='1') then. Can anyone explain to me in plain English why is this happening and a solution to it so I won't have the same kind problems again? Thanks in advance
You have default signal assignments before the if rst='1' then clause.
That means, when rst returns to 0 (in simulation) these default assignments will execute, and delete the reset values of those signals.
XST is telling you that the hardware can't actually do that.
The solution is to delete those default assignments, which will restore this process to a standard form. Then think carefully about what they were for and how to keep their functionality if you need to.
The traditional place for such assignments is immediately after the elsif rising_edge(clk) then clause, where they will be executed on every clock edge (provided Rst is low) then overridden by any other assignments that are executed yb the process.
I am using the following VHDL to take a 100 Mhz clock and put out a 25 Mhz clock. :
process(clk, reset)
variable count : integer range 0 to 2;
begin
if (reset = '1') then
clock_25MHz <= '0';
count := 0;
elsif rising_edge(clk) then
count := count+1;
if(count >= 2) then
clock_25MHz <= not clock_25MHz;
count := 0;
end if;
end if;
end process;
It is giving me this warning:
"WARNING:Xst:1293 - FF/Latch count_1 has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process."
I don't understand why its happening. Can anyone shed some light on this for me? Thanks!
You don't need 2 bits of count. A single flip flop is enough.
If you add an integer signal CNT that's assigned count (allowing me to see it on a waveform with ghdl):
library ieee;
use ieee.std_logic_1164.all;
entity clk_div is
end entity;
architecture foo of clk_div is
signal clk: std_logic := '0';
signal reset: std_logic := '1';
signal clock_25MHz: std_logic;
signal CNT: integer;
begin
CLKDIV:
process(clk,reset)
variable count: integer range 0 to 2;
begin
if (reset = '1') then
clock_25MHz <= '0';
count:=0;
elsif rising_edge(clk) then
count:=count+1;
if(count>=2) then
clock_25MHz <= not clock_25MHz;
count:=0;
end if;
end if;
CNT <= count;
end process;
CLOCK:
process
begin
wait for 5 ns;
clk <= not clk;
if Now > 200 ns then
wait;
end if;
end process;
UNRESET:
process
begin
wait for 20 ns;
reset <= '0';
wait;
end process;
end architecture;
You find:
The count always shows up as either 0 or 1 and not 2 or 3, because you assign it to 0 when ever its 2 or greater. It never shows up as 2 on a clock edge.
Is that correct? Why yes it is. If you clock at the waveform with clock_25MHz lasting 4 100 Mhz clocks it works perfectly. You're process is doing something that's not necessary, count doesn't need a range of 0 to 2, (requiring two flip flops).
Change the evaluation order for count so clock_25MHz is toggled when count = 1, then toggle count. Change the range of count to 0 to 1 or better still make it type std_logic.
-- signal CNT: integer;
signal toggle_ff: std_logic;
begin
CLKDIV:
process(clk,reset)
--variable count: integer range 0 to 2;
variable toggle: std_logic;
begin
if (reset = '1') then
clock_25MHz <= '0';
-- count:=0;
toggle := '0';
elsif rising_edge(clk) then
-- count:=count+1;
-- if(count>=2) then
if toggle = '1' then
clock_25MHz <= not clock_25MHz;
-- count:=0;
end if;
toggle := not toggle;
end if;
-- CNT <= count;
toggle_ff <= toggle;
end process;
Which gives:
You could also use a signal in the process statement instead of a variable. In my example code rename toggle_ff to toggle, remove the variable toggle declaration and remove the signal assignment statement to toggle_ff. The reason this will work seamlessly is because you evaluate the output of the toogle FF before it is toggled.
The warning occurs since the state in count implemented as FF/Latch by Xilinx
goes 0, 1, 0, 1, ..., and only an internal combinatorial value of count ever
gets the value 2, thus any bit 1 in the count state will always be 0, as the
warning says "FF/Latch count_1 has a constant value of 0 in block".
You can also see this since the code can be rewritten with reduced ´count´
range as 0 to 1, if the count increment is placed inside the if like:
process(clk, reset)
variable count : integer range 0 to 1;
begin
if (reset = '1') then
clock_25MHz <= '0';
count := 0;
elsif rising_edge(clk) then
if (count = 1) then
clock_25MHz <= not clock_25MHz;
count := 0;
else
count := count + 1;
end if;
end if;
end process;
But based on the specific requirement of doing a division by 4 from a 100 MHz
to a 25 MHz clock, it may be more obvious creating an intermediate 50 MHz clock
instead of count, with code like:
process(clk, reset)
variable clock_50MHz : std_logic;
begin
if (reset = '1') then
clock_25MHz <= '0';
clock_50MHz := '0';
elsif rising_edge(clk) then
clock_50MHz := not clock_50MHz;
if clock_50MHz = '1' then
clock_25MHz <= not clock_25MHz;
end if;
end if;
end process;