I was trying to count pixels based on the signals from the AXI stream signals like tuser and tlast. I wrote this:
p_pixelcount : process (s_clk)
variable v_hcount : integer := 1;
variable v_linecount: integer:= 1;
begin
if (rising_edge(s_clk)) then
if (s_maxis_s_tvalid_out = '1')and (s_maxis_s_tready_in = '1') then
if ( rising_edge(s_maxis_s_tuser_out) ) then
v_hcount := 0;
v_linecount := 0;
else
v_hcount := v_hcount + 1;
end if;
if (s_maxis_s_tlast_out = '1') then
v_hcount := 0;
v_linecount := v_linecount + 1;
end if;
end if;
end if;
end process p_pixelcount;
I received the following simulation outputs
My questions:
When tuser is high, shouldn't the v_hcount be 0?
Is it allowed to use two rising_edge(signal) conditions on different signals in the same process?
I want to count till tlast and then in the next cycle the count is set zero. Is it possible to do this without using a signal?
Thanks
First off: don't make v_hcount and v_linecount variables. They are clocked, so need to be registered: use signals for that. (for synthesizable code)
No, you cannot use rising_edge twice in a process like this. If you want to detect a 0->1 transition, you need to do that in the (correct) clock domain. E.g.
s_maxis_s_tuser_out_delay <= s_maxis_s_tuser_out when rising_edge(s_clk);
s_maxis_s_tuser_out_rising <=
'1' when s_maxis_s_tuser_out = '1' and s_maxis_s_tuser_out_rising = '0'
else '0';
but in this case you should probably just use
if (s_maxis_s_tuser_out = '1') then
v_hcount <= 1;
v_linecount <= 0;
else
v_hcount <= v_hcount + 1;
if (s_maxis_s_tlast_out = '1') then
v_hcount <= 0;
v_linecount <= v_linecount + 1;
end if;
end if;
Why do you initialize the v_hcount and v_linecount at 1, but reset them to 0?
Related
I want to make a UART receiver that reads 8 consecutives bits with a parity bit at the end and with a simple stop bit. My FPGA have a clock of 100Mhz and the data that are transmitted to the uart have a rate of 56700 bauds. The dividing factor is 1736 (56700 * 1736 ≈ 100Mhz). The two outputs are the message of the input decoded by the uart and an error signal that indicates if the uart have correctly read the input. This is what I have :
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity uart_receiver is
generic (
clksPerBit : integer := 1736 -- Needs to be set correctly
);
port (
clk : in std_logic;
clk_en_uart : in std_logic ;
reset : in std_logic;
uart_rx : in std_logic;
error : out std_logic;
char : out std_logic_vector(7 downto 0)
);
end uart_receiver;
architecture uart_receiver_arch of uart_receiver is
type etat is (init, start_bit, receiving_bits, parity_bit,
stop_bit );
signal current_state : etat := init ;
signal error_signal : std_logic := '0';
signal clk_count : integer range 0 to clksPerBit-1 := 0;
signal bit_index : integer range 0 to 7 := 0; -- 8 Bits Total
signal data_byte : std_logic_vector(7 downto 0) := (others => '0');
begin
process (clk_en_uart)
begin
if rising_edge(clk_en_uart) then
end if;
end process;
process (clk,reset)
variable check_parity : integer range 0 to 7 := 0;
begin
if (reset = '1') then
current_state <= init;
error_signal <= '0';
clk_count <= 0;
bit_index <= 0;
data_byte <= (others => '0');
elsif rising_edge(clk) then
case current_state is
when init =>
clk_count <= 0;
Bit_Index <= 0;
if uart_rx = '0' then -- Start bit detected
current_state <= start_bit;
else
current_state <= init;
end if;
when start_bit =>
if clk_count = (clksPerBit-1)/2 then
if uart_rx = '0' then
clk_count <= 0; -- reset counter since we found the middle
current_state <= receiving_bits;
else
current_state <= init;
end if;
else
clk_count <= clk_count + 1;
current_state <= start_bit;
end if;
when receiving_bits =>
if clk_count < clksPerBit-1 then
clk_count <= clk_count + 1;
current_state <= receiving_bits;
else
clk_count <= 0;
data_byte(bit_index) <= uart_rx;
if bit_index < 7 then
bit_index <= bit_index + 1;
current_state <= receiving_bits ;
else
bit_index <= 0;
current_state <= parity_bit;
end if;
end if;
when parity_bit =>
if clk_count < clksPerBit-1 then
clk_count <= clk_count + 1;
current_state <= parity_bit;
else
for k in 0 to 7 loop
if ( data_byte(k) = '1' ) then
check_parity := check_parity + 1 ;
end if;
end loop;
if((uart_rx = '1' and check_parity mod 2 = 0) or (uart_rx = '0' and check_parity mod 2 = 1)) then
error_signal <= '1' ;
else
error_signal <= '0';
end if ;
current_state <= stop_bit;
end if;
when stop_bit =>
if clk_count < clksPerBit-1 then
clk_count <= clk_count + 1;
current_state <= stop_bit ;
else
clk_count <= 0;
current_state <= init;
end if;
when others =>
current_state <= init;
end case;
end if;
char <= data_byte ;
error <= error_signal ;
end process;
end uart_receiver_arch;
So there's a phase shift between the data that is transmitted to the uart and his clock. If there's a phase shift, I'm not reading the data at the right time. I think that this code is sufficient to solve this problem. But, I've created a clock_divider and I can't seem to find a way to use it in this code. This is my clock divider :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clock_divider is
generic (divfactor : positive := 1736);
Port (clk,clk2, reset : in STD_LOGIC ;
clkdiv, activationsig : out STD_LOGIC );
end clock_divider;
architecture clock_divider_arch of clock_divider is
begin
process(clk,reset)
variable clksigv : std_logic := '0' ;
variable activationsigv : std_logic := '0' ;
variable count : integer := 0 ;
begin
if (reset = '1') then
clksigv := '0' ;
activationsigv := '0' ;
count := 0 ;
elsif ( rising_edge(clk) ) then
count := count + 2 ;
if (activationsigv = '1') then
activationsigv := '0';
end if;
if ( count >= divfactor - 1 ) then
clksigv := not(clksigv) ;
if ( clksigv = '1' ) then
activationsigv := '1' ;
end if;
count := 0 ;
end if ;
end if ;
clkdiv <= clksigv ;
activationsig <= activationsigv;
end process ;
end clock_divider_arch;
The outputs of this clock divider are the clock divided and the activation signal that, when it is at '1', I have to read the data in the uart. So, the two outputs should also be inputs of the uart. In the uart_recevier, clk_en_uart is actually the clock divided, but I'm not using it because I don't know how.
I think that the solution is to 'activate' this divided clock when I enter in the start_bit case so that I have two clocks with the same phase and the same frequency, but I also think that it impossible to set a phase for a clock.
I'm not sure that I've clearly adressed my problem. If there's something that you don't understand in my code or in my explanation, feel free to ask questions.
Thank you for your help, hoping that I find a solution.
Sounds like the suggested solution is complicated for this problem.
A usual approach is that the receiver justs look for the falling edge of the start bit, then count for half a bit time (1736 / 2 cycles in your case), then samples the start bit value there, and subsequently samples the data, parity and stop bit values after each full bit time (1736 cycles in your case). After that start over looking for a new falling edge of the start bit.
The difference between the transmitter and receiver frequencies are then (usually) so small that the sample time will be practically in the middle for messages of only 11 bits at relative low bitrate, and the counter restart at falling edge of start bit ensures that any effect of long time frequency difference is removed.
I am using code from this website code:
entity triangular is
port (clk : in std_logic;
wave_out : out std_logic_vector(7 downto 0);
reset :in std_logic
);
end triangular;
architecture Behavioral of triangular is
signal count,count2 : integer := 0;
signal direction : std_logic := '0';
begin
process(clk,reset)
begin
if(reset = '1') then
count <= 0;
count2 <= 129;
elsif(rising_edge(clk)) then
--"direction" signal determines the direction of counting - up or down
if(count = 253) then
count <= 0;
if(direction = '0') then
direction <= '1';
count2 <= 126;
else
direction <= '0';
count2 <= 129;
end if;
else
count <= count + 1;
end if;
if(direction = '0') then
if(count2 = 255) then
count2 <= 0;
else
count2 <= count2 + 1; --up counts from 129 to 255 and then 0 to 127
end if;
else
if(count2 = 255) then
count2 <= 0;
else
count2 <= count2 - 1; --down counts from 126 to 0 and then 255 to 128
end if;
end if;
end if;
end process;
wave_out <= conv_std_logic_vector(count2,8);
end Behavioral;
and I am getting output in digital format but I want to get output as given in the website link. How can I do that? I am new to VHDL working this as assignment.
(click to enlarge)
In Xilinx ISE simulator simulation result only in digital value instead of ISim you can use ModelSim simulator
In that ModelSim simulator Analog Data option Available
In Vivado Simulator Also have analog data view option
I am trying to run a simple counter(v_bincount) starting from 0 to the time when the s_saxis_tlast goes high. It starts counting when s_saxis_tuser_in is high. It starts from 0 however the value of the counter remains 0 for one more clock cycle even though v_bincount is a shared variable and not a signal.
p_count: process(clk)
begin
if (rising_edge (clk)) then
if (s_saxis_tvalid_in = '1')and (s_saxis_tready_out = '1') then
if(s_saxis_tuser_in ='1') then
v_bincount1 := 0;
v_idcount1 := 0;
else
if (s_saxis_tlast_in = '0') then
v_bincount1 := v_bincount1 + 1;
else
v_bincount1 := 0;
v_idcount1 := v_idcount1 + 1;
end if;
end if;
else
v_bincount1 := 0;
v_idcount1 := 0;
end if;
end if;
end process p_count;
The simulation is what you would assume. On the lowering edge of the tuser_in, it is still '1' at the clock edge.
I would suggest not to use shared variable here. Instead, have a combinatorial counter with signals which increment the value according to your wishes and then clocked process to assign the value to a register e.g.:
p_count_r : process(clk)
begin
if (rising_edge (clk)) then
s_bin_count_r <= s_bin_count;
s_id_count_r <= s_id_count;
end if;
end process p_count_r;
and in the combinatorial process use the s_bin_count_r on the right-hand side.
i'm working on a project using vhdl to configure a fpga board spartan 3E. what i have to do is a genius puzzle, in my main code there is a state machine to control the logic.
everything works well when i simulate the code using xilinx simulator but when i run the .bit file to the FPGA board what happens is that the first led of the sequence turns on and then turns off, this should happen but then when i click the right button it just stop working and the next sequence is never shown.
of course there is a issue of deboucing the buttons, and that's the reason i'm using a counter to prevent the repic to bug the system.
i'm working hard on this code to function but this issue doesn't go away, maybe i'm doing something wrong i don't know or i'm not doing something i should.
here is my main code, which is the state machine and a clock proccess with the counter.
Flag_conte = starts ou blocks the counter
Flag_estou_contando = 1=counting, 0= not counting, 3= just finished count.
BCD = board buttons IN
LEDs = corresponds to 4 leds that will show the sequence in the game
entity Algoritmo is
port(
clk: in std_logic;
BCD: in std_logic_vector (3 downto 0);
botaoStart: in std_logic;
botaoReset: in std_logic;
seven_seg: out std_logic_vector(6 downto 0);
anode: out std_logic_vector(3 downto 0);
LEDS: out std_logic_vector(3 downto 0)
);
END Algoritmo;
architecture Behavioral of Algoritmo is
subtype state_type is integer range 5 downto 0;
signal state, nextstate: state_type:=0;
signal Inicio, nclk: std_logic:= '0';
--variable posicaoAtual: integer :=0;
type mem1 is array (0 to 13) of std_logic_vector (3 downto 0);
constant vetorSequencia: mem1 := ( "0001", "0010", "0100", "1000", "0001", "0010", "0100", "1000", "0001", "0010", "0100", "1000", "0001", "0010");
constant generic1hz: integer:= 12_500_000;
signal t3count:integer:=0;
signal posA, posB, signalScore, Flag_conte,
Flag_estou_contando:integer:=0;
signal valor: integer :=12_500_000;
Begin
-------------
process (state,BCD,botaoStart,Flag_estou_contando)
variable Pos: integer :=0;
variable score: integer:=0;
variable posicaoAtual: integer:=0;
variable tentativa: std_logic_vector (3 downto 0);
begin
case state is
when 0 => if (botaoStart = '0')
then nextstate <= 0;-- estado idle, esperando entrada do tclado,led1=1;
else nextstate <= 1;
end if;
when 1 =>-- if(Flag_estou_contando =0)then
if(nextstate=2)then
Flag_conte <=0;
nextstate <= 2;
else if (nextstate/=2)then
if (posicaoAtual < score)then
if(Flag_estou_contando=0)then
LEDS <= vetorSequencia(posicaoAtual);
posA <= posicaoAtual;
Flag_conte<=1;
valor<=10_000_000;
else if(Flag_estou_contando=1)then
LEDS <=vetorSequencia(posicaoAtual);
else if (Flag_estou_contando=3)then
--posicaoAtual:=0;
posicaoAtual := posicaoAtual + 1;
posA <= posicaoAtual;
nextstate <=1;
Flag_conte<=0;
end if;end if;end if;
else if(posicaoAtual = score)then
if(Flag_estou_contando=0)then
Flag_conte<=1;
valor<=10_000_000;
-- posicaoAtual :=0;
posA <= posicaoAtual;
else if(Flag_estou_contando=1)then
LEDS <=vetorSequencia(posicaoAtual);
nextstate<=1;
else if(Flag_estou_contando=3)then
posicaoAtual:=0;
posA <= posicaoAtual;
Flag_conte<=0;
nextstate <= 2;
end if;end if;end if;
end if;end if;
Flag_conte <=1;
end if;end if;
when 2 => --if(Flag_estou_contando=0)then
if (BCD = "0000")then
if(Flag_estou_contando=0)then
LEDS <= "0000"; --nextstate <= 2;
else if (Flag_estou_contando=1)then
nextstate<=2;
else if (Flag_estou_contando=3)then
Flag_conte <= 0;
nextstate<=3;
end if;end if;end if;
else if(BCD /= "0000")then
if(Flag_estou_contando=0)then
Flag_conte<=1;
valor<=200_000_000;
tentativa := BCD;
LEDS <= tentativa;
else if(Flag_estou_contando=3)then
nextstate <= 3;
else if(Flag_estou_contando=1)then
LEDS <= tentativa;
nextstate <=2;
end if;end if;end if;
end if;end if;
when 3 => if (vetorSequencia(Pos) = tentativa)then
if (Pos < score)then
nextstate <= 2;
Pos := Pos + 1;
posB <= Pos;
else if(Pos = score)then
score := score + 1;
signalScore <= score;
nextstate <= 1;
Pos := 0;
if (score = 15)-- if score =15 finish game
then nextstate <= 5;
end if;--end if
end if;end if;
else -- se estiver errado, perde o jogo
nextstate <= 4; -- goes to game over
end if;
when 4 => if (botaoReset = '1') -- game over
then nextstate <= 4;-- "U LOST nOOB"
elsif (botaoReset = '0')
then nextstate <= 0; --
end if;
when 5 => if (botaoReset = '1') -- jogo ganho
then nextstate <= 5; -- "GG"
elsif (botaoReset = '0')
then nextstate <= 0;
end if;
end case;
end process;
process (clk, Flag_conte)
variable sum, count :integer:=0;
begin
if rising_edge(clk) then
if(Flag_estou_contando = 0) then
if (Flag_conte = 1) then
count :=0;
Flag_estou_contando <=1;
end if;
end if;
if(Flag_estou_contando=3) then
if(Flag_conte =0)then
Flag_estou_contando <= 0;
else
Flag_estou_contando <=3;
end if;
end if;
if (Flag_estou_contando =1)then
if(count < valor)then
count := count + 1;
else
count:=0;
Flag_estou_contando <=3;
end if;
end if;
sum := sum +1;
if(sum = generic1hz)then -- 1hz generate
state <= nextstate;
nclk <= not nclk;
sum := 0;--restart count for 1hz generate
end if;
end if;
end process;
end Behavioral;
if i wasnt clear, please let me know i will try to explain better, if anyone could help i would be very greatful, thank you for your time.
You should try post place & route simulation to verify whats happen:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/pp_p_process_simulate_post_place.htm
With some family device you can use chipscope technology to debug:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx10/isehelp/ise_c_process_analyze_design_using_chipscope.htm
Sorry for my English.
Regards.
I am writing a little program for use on my Zybo FPGA, its supposedly a variable frequency divider with 10 different steps.
However on the last line when I try to output my clock to an LED for testing purposes it gives me this error: Line 137: statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition
Here is my code
entity StappenMotor is
Port ( Reset, CLK : in STD_LOGIC;
X1, X2 : in STD_LOGIC;
Z1 : out STD_LOGIC);
end StappenMotor;
architecture Behavioral of StappenMotor is
signal speed : integer := 0;
signal puls : STD_LOGIC;
begin
speed_proc: process(X1, X2) is
begin
if (rising_edge(X1) and speed < 10) then
speed <= speed + 1;
elsif (rising_edge(X2) and speed > 0) then
speed <= speed - 1;
end if;
end process speed_proc;
freq_proc: process(CLK) is
variable int : integer := 0;
begin
if rising_edge(CLK) then
int := int + 1;
end if;
case speed is
when 0 =>
if int = 250000000 then
puls <= '1';
int := 0;
else puls <= '0';
end if;
when 1 =>
if int = 200000000 then
puls <= '1';
int := 0;
else puls <= '0';
end if;
when 2 =>
if int = 175000000 then
puls <= '1';
int := 0;
else puls <= '0';
end if;
when 3 =>
if int = 150000000 then
puls <= '1';
int := 0;
else puls <= '0';
end if;
when 4 =>
if int = 125000000 then
puls <= '1';
int := 0;
else puls <= '0';
end if;
when 5 =>
if int = 100000000 then
puls <= '1';
int := 0;
else puls <= '0';
end if;
when 6 =>
if int = 75000000 then
puls <= '1';
int := 0;
else puls <= '0';
end if;
when 7 =>
if int = 62500000 then
puls <= '1';
int := 0;
else puls <= '0';
end if;
when 8 =>
if int = 50000000 then
puls <= '1';
int := 0;
else puls <= '0';
end if;
when 9 =>
if int = 35000000 then
puls <= '1';
int := 0;
else puls <= '0';
end if;
when 10 =>
if int = 25000000 then
puls <= '1';
int := 0;
else puls <= '0';
end if;
when others =>
if int = 10000000 then
puls <= '1';
int := 0;
else puls <= '0';
end if;
end case;
end process freq_proc;
test: process(puls) is
begin
if rising_edge(puls) then
Z1 <= '1';
else Z1 <= '0';
end if;
end process test;
end Behavioral;
Error occurs on the line:
if rising_edge(puls) then
Anyone got a clue?
Kind regards.
All of your processes have some issues, though the compiler may not complain about them as loudly as the one in test.
In speed_proc, you are qualifying rising_edge() with an additional comparison. I would recommend nesting if statements instead (put the comparison if inside the rising_edge() if). You're also trying to clock the same register with 2 separate clocks. You probably need to find a different way to do this.
In freq_proc, only your variable increment is inside the rising_edge() check - I don't see a reason not to put the rest in as well. It's more standard, and it should generally lead to fewer unexpected problems.
In test, as #Chiggs mentioned, what you're trying to accomplish is invalid. If you want to toggle Z1 every clock cycle, you can do:
if rising_edge(puls) then
Z1 <= not Z1;
end if;
(For simulation, you'd need to initialize Z1 to see a valid output.)
The problem is the whole test process, not just the single line you've mentioned.
test: process(puls) is
begin
if rising_edge(puls) then
Z1 <= '1';
else Z1 <= '0';
end if;
end process test;
If you think about what you've described here, you're asking to drive Z1 high whenever there's a rising edge on the clock and drive it low whenever puls changes but isn't a rising edge (which includes Z->1, 1->0, Z->0 transitions).
This generally isn't possible in an FPGA and therefore is not synthesisable, hence the tool complaining.