Vhdl rising_edge statement not synthesizable - vhdl

Question

I am writing a little program for use on my Zybo FPGA, its supposedly a variable frequency divider with 10 different steps.
However on the last line when I try to output my clock to an LED for testing purposes it gives me this error: Line 137: statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition
Here is my code
entity StappenMotor is
Port ( Reset, CLK : in STD_LOGIC;
X1, X2 : in STD_LOGIC;
Z1 : out STD_LOGIC);
end StappenMotor;
architecture Behavioral of StappenMotor is
signal speed : integer := 0;
signal puls : STD_LOGIC;
begin
speed_proc: process(X1, X2) is
begin
if (rising_edge(X1) and speed < 10) then
speed <= speed + 1;
elsif (rising_edge(X2) and speed > 0) then
speed <= speed - 1;
end if;
end process speed_proc;
freq_proc: process(CLK) is
variable int : integer := 0;
begin
if rising_edge(CLK) then
int := int + 1;
end if;
case speed is
when 0 =>
if int = 250000000 then
puls <= '1';
int := 0;
else puls <= '0';
end if;
when 1 =>
if int = 200000000 then
puls <= '1';
int := 0;
else puls <= '0';
end if;
when 2 =>
if int = 175000000 then
puls <= '1';
int := 0;
else puls <= '0';
end if;
when 3 =>
if int = 150000000 then
puls <= '1';
int := 0;
else puls <= '0';
end if;
when 4 =>
if int = 125000000 then
puls <= '1';
int := 0;
else puls <= '0';
end if;
when 5 =>
if int = 100000000 then
puls <= '1';
int := 0;
else puls <= '0';
end if;
when 6 =>
if int = 75000000 then
puls <= '1';
int := 0;
else puls <= '0';
end if;
when 7 =>
if int = 62500000 then
puls <= '1';
int := 0;
else puls <= '0';
end if;
when 8 =>
if int = 50000000 then
puls <= '1';
int := 0;
else puls <= '0';
end if;
when 9 =>
if int = 35000000 then
puls <= '1';
int := 0;
else puls <= '0';
end if;
when 10 =>
if int = 25000000 then
puls <= '1';
int := 0;
else puls <= '0';
end if;
when others =>
if int = 10000000 then
puls <= '1';
int := 0;
else puls <= '0';
end if;
end case;
end process freq_proc;
test: process(puls) is
begin
if rising_edge(puls) then
Z1 <= '1';
else Z1 <= '0';
end if;
end process test;
end Behavioral;
Error occurs on the line:
if rising_edge(puls) then
Anyone got a clue?
Kind regards.

Answer 1

All of your processes have some issues, though the compiler may not complain about them as loudly as the one in test.
In speed_proc, you are qualifying rising_edge() with an additional comparison. I would recommend nesting if statements instead (put the comparison if inside the rising_edge() if). You're also trying to clock the same register with 2 separate clocks. You probably need to find a different way to do this.
In freq_proc, only your variable increment is inside the rising_edge() check - I don't see a reason not to put the rest in as well. It's more standard, and it should generally lead to fewer unexpected problems.
In test, as #Chiggs mentioned, what you're trying to accomplish is invalid. If you want to toggle Z1 every clock cycle, you can do:
if rising_edge(puls) then
Z1 <= not Z1;
end if;
(For simulation, you'd need to initialize Z1 to see a valid output.)

Answer 2

The problem is the whole test process, not just the single line you've mentioned.
test: process(puls) is
begin
if rising_edge(puls) then
Z1 <= '1';
else Z1 <= '0';
end if;
end process test;
If you think about what you've described here, you're asking to drive Z1 high whenever there's a rising edge on the clock and drive it low whenever puls changes but isn't a rising edge (which includes Z->1, 1->0, Z->0 transitions).
This generally isn't possible in an FPGA and therefore is not synthesisable, hence the tool complaining.