This is a question about memory organization which I have had very difficulty to understand,
Assume we have an N-way set associative cache with the capacity 4096bytes. The
set field size of the address is 7 bits and the tag field 21 bits. If we assume that
the cache is used together with a 32-bit processor, what is then the block size (in
bytes), how many valid bits does the cache contain, and what is the associativity of
the cache?
Here are some equation that is good to know in order to solve question of these type.
Parameter to know
C = cache capacity
b = block size
B = number of blocks
N = degree of associativity
S = number of set
tag_bits
set_bits (also called index)
byte_offset
v = valid bits
Equations to know
B = C/b
S = B/N
b = 2^(byte_offset)
S = 2^(set_bits)
Memory Address
|___tag________|____set___|___byte offset_|
Now to the question
known:
C = 4096 bytes
set_bits = 7
tag_bits = 21
32 bits address field
Asked:
b?
N?
v?
Simply subtract the tag_bits and set_bits from the 32 bit field this gives you the byte_offset.
byte_offset = 32-21-7 = 4 bits
b = 2^4 = 16 bytes
S = 2^7 = 128 set
B = C/b = 4096/16 = 256
N = B/S = 256/128 = 2
v = B = 256 valid bits
So, we have the following information about the processor and the cache -
Cache Size = 4096 B
Address bits = 32
Index bits = 7
Tag bits = 21
From the above information you can quickly calculate the number of bits required for the offset field -
Offset bits = Address bits - Tag bits - Index bits
Offset bits = 32 - 21 - 7 = 4
Offset bits = 4
Using the offset bits, you can find the block size, 2**offset bits
Block Size = 16 bytes
Next thing is the associativity of the cache
We know that the index bits = 7.
This means we have 128 blocks. Each block is 16 bytes wide.
Therefore, the number of ways in the cache would be -
Number of ways = Cache Size / (number of blocks * block Size)
Number of ways = 2
Hence the associativity is 2.
Regarding the number of valid bits. Each block requires a valid bit. Hence the number of valid bits would be -
Valid bits = 128*2
Valid bits = 256
Related
I am studying for my computer architecture exam that is due tomorrow and am stuck on a practice exercise regarding tag size and the total number of cache bits. Here is the question:
Question 8:
This question deals with main and cache memory only.
Address size: 32 bits
Block size: 128 items
Item size: 8 bits
Cache Layout: 6 way set associative
Cache Size: 192 KB (data only)
Write Policy: Write Back
Answer: The tag size is 17 bits. The total number of cache bits is 1602048.
I know that this a failry straight-forward exercise, but I seem to be lacking the proper formulas. I also know that the structure of a N set way associative is |TAG 25 bits|SET 2 bits|OFFSET 5 bits|. And that Tag size = AddrSize - Set - Offset (- item size if any) thus giving the answer of 17 bits tag size.
However, how do I calculate the total number of cache bits please?
cache size in bytes: 192*1024 = 196608
number of blocks: 196608 / 128 = 1536
number of sets: 1536 / 6 = 256
set number bits: log2(256) = 8
offset number bits: log2(128) = 7
tag size: 32-(8+7) = 17
metadata: valid+dirty = 2 bits
total tag + metadata: (17+2)*1536 = 29184 bits
total data: 1536*128*8 = 1572864 bits
total size: 29184 + 1572864 = 1,602,048
There could also be bits used for the replacement policy, but we can assume it's random to make the answer work.
i am really confused on the topic Direct Mapped Cache i've been looking around for an example with a good explanation and it's making me more confused then ever.
For example: I have
2048 byte memory
64 byte big cache
8 byte cache lines
with direct mapped cache how do i determine the 'LINE' 'TAG' and "Byte offset'?
i believe that the total number of addressing bits is 11 bits because 2048 = 2^11
2048/64 = 2^5 = 32 blocks (0 to 31) (5bits needed) (tag)
64/8 = 8 = 2^3 = 3 bits for the index
8 byte cache lines = 2^3 which means i need 3 bits for the byte offset
so the addres would be like this: 5 for the tag, 3 for the index and 3 for the byte offset
Do i have this figured out correctly?
Do i figured out correctly? YES
Explanation
1) Main memmory size is 2048 bytes = 211. So you need 11 bits to address a byte (If your word size is 1 byte) [word = smallest individual unit that will be accessed with the address]
2) You can calculating tag bits in direct mapping by doing (main memmory size / cash size). But i will explain a little more about tag bits.
Here the size of a cashe line( which is always same as size of a main memmory block) is 8 bytes. which is 23 bytes. So you need 3 bits to represent a byte within a cashe line. Now you have 8 bits (11 - 3) are remaining in the address.
Now the total number of lines present in the cache is (cashe size / line size) = 26 / 23 = 23
So, you have 3 bits to represent the line in which the your required byte is present.
The number of remaining bits now are 5 (8 - 3).
These 5 bits can be used to represent a tag. :)
3) 3 bit for index. If you were trying to label the number of bits needed to represent a line as index. Yes you are right.
4) 3 bits will be used to access a byte withing a cache line. (8 = 23)
So,
11 bits total address length = 5 tag bits + 3 bits to represent a line + 3 bits to represent a byte(word) withing a line
Hope there is no confusion now.
This is a question from a Computer Architecture exam and I don't understand how to get to the correct answer.
Here is the question:
This question deals with main and cache memory only.
Address size: 32 bits
Block size: 128 items
Item size: 8 bits
Cache Layout: 6 way set associative
Cache Size: 192 KB (data only)
Write policy: Write Back
What is the total number of cache bits?
In order to get the number of tag bits, I find that 7 bits of the address are used for byte offset (0-127) and 8 bits are used for the block number (0-250) (250 = 192000/128/6), therefore 17 bits of the address are left for the tag.
To find the total number of bits in the cache, I would take (valid bit + tag size + bits per block) * number of blocks per set * number of sets = (1 + 17 + 1024) * 250 * 6 = 1,536,000. This is not the correct answer though.
The correct answer is 1,602,048 total bits in the cache and part of the answer is that there are 17 tag bits. After trying to reverse engineer the answer, I found that 1,602,048 = 1043 * 256 * 6 but I don't know if that is relevant to the solution because I don't know why those numbers would be used.
I'd like if someone could explain what I did wrong in my calculation to get a different answer.
From what I could find online, the Cache index is the same for every cache block/line. The notes that our instructor gave us seem to contradict this.
Cache index ( or some times called set bits) are the (block address) module (number of blocks in the cache).
If the number of entries in the cache is a power of 2, then modulo can be
computed simply by using the low-order log2 (cache size in blocks) bits of the
address.
In your case direct mapped cache.
A 4-block cache uses the two lowest bits (4 = 2^2 ) of the block
address.
(block address) cache index
0000 mod 4 = 00
1000 mod 4 = 00
0000 mod 4 = 00
0110 mod 4 = 10
1000 mod 4 = 00
Here are some equations and parameter that is good to know in order to solve cache problems in general.
Parameter to know
C = cache capacity
b = block size
B = number of blocks
N = degree of associativity
S = number of set
tag_bits
set_bits (also called index)
byte_offset
v = valid bits
Equations to know
B = C/b
S = B/N
b = 2^(byte_offset)
S = 2^(set_bits)
Memory Address
|___tag________|____set___|___byte offset_|
I'm struggling to solve this question, I've looked around but all of the similar questions are more advanced than mine, making use of logs, it's more advanced than we've done in our class. Here's the question:
Suppose you have a 4-way set associative cache which has in total
4096 bytes of cache memory and each cache line is 128 bytes. How many
sets are there is this cache? If memory is byte addressable and addresses
are 16 bits then how many bytes are used for the tag?
Here's what I have so far:
4096/128 = num lines
4096/128/4 = 8 = num sets (each set is 4 lines in 4-way set assoiative)
So, need 3 bits to choose set (2^3=8)
We have 16-3 = 13 bits left for the tag and word.
Because the question says that memory is byte addressable, I think that this means that the word is 8 bits (= 1 byte) long, and thus the tag is 16-3-8 = 5 bits long.
Although I'm not quite sure about this. Does anyone have a solution to this problem?
If memory is byte addressable
This statement just tell us that the main memory is byte addressable ie., architectures where data can be accessed 8 bits at a time, irrespective of the width of the data and address buses.
This doesn't affect the number of bit the tag has.
Solution:
4-way set associative
Total cache memory = 4096 bytes
Block size(cache line) = 128 byte
Number of cache line = 4096 / 128 = 32 lines
Number of sets in cache = 32 / 4 = 8 sets
╔════════════════════════════╗
║ 16 bit address ║
╠══════════╤════════╤════════╣
║ tag bit? │ 3 bits │ 7 bits ║
╚══════════╧════════╧════════╝
Word offset = log28 = 3 bits
Set offset = log2128 = 7 bits
Answer:
Tag bit = 16 - ( 3 + 7 ) = 6 bits
╔══════════════════════════╗
║ 16 bit address ║
╠════════╤════════╤════════╣
║ 6 bits │ 3 bits │ 7 bits ║
╚════════╧════════╧════════╝
cache capacity is 4096 bytes means (2^12) bytes .
Each Block/line in cache contains (2^7) bytes
-therefore number of lines or blocks in cache is:(2^12)/(2^7)=2^5 blocks or lines in a cache
As it is 4 way set associative, each set contains 4 blocks, number of sets in a cache is :
(2^5)/2^2 = 2^3 sets are there. so from these we got to know that 3 bits are required for adressing set offset.
As it is byte addressable , to address a byte offset we require 7 bits as we have 128(2^7) bytes in each block.
Remaining 6 bits will be allocated for tag.