You see, I've already finished to describe an ALU on vhdl with modelsim, however the testbench seems to not update the solution, when I see the simulation the circuit 32 bit response always says "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" I dont know what did i wrote wrong on the testbench also there is a warning on the compiler about the circuit response which says
** Warning: (vsim-8683) Uninitialized out port /alu_tb/ALU_test/res(32 downto 0) has no driver.
This port will contribute value (UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU) to the signal network.
and here is the testbench code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ALU_tb is
end ALU_tb;
architecture bhv_ALU_tb of ALU_tb is
component ALU
port(
a, b: in std_logic_vector(31 downto 0);
c: in std_logic;
s: in std_logic_vector(3 downto 0);
res: out std_logic_vector(32 downto 0));
end component;
signal a, b: std_logic_vector(31 downto 0);
signal c: std_logic;
signal s: std_logic_vector(3 downto 0);
signal re: std_logic_vector(32 downto 0);
begin
ALU_test: ALU port map (a => a, b => b, c => c, s => s, res => re);
process begin
b <= "00000000000010100111010100011110";
a <= "00000000011010000100110011101110";
c <= '0';
s <= "1111";
wait for 2 ns;
b <= "00000000000010100111010100011110";
a <= "00000000011010000100110011101110";
c <= '0';
s <= "0100";
wait for 2 ns;
s <= "0000";
wait for 2 ns;
s <= "0001";
wait for 2 ns;
s <= "0010";
wait for 2 ns;
s <= "0011";
wait for 2 ns;
s <= "0100";
wait for 2 ns;
s <= "0101";
wait for 2 ns;
s <= "0110";
wait for 2 ns;
s <= "0111";
wait for 2 ns;
s <= "1000";
wait for 2 ns;
s <= "1001";
wait for 2 ns;
s <= "1010";
wait for 2 ns;
s <= "1011";
wait for 2 ns;
s <= "1100";
wait for 2 ns;
s <= "1101";
wait for 2 ns;
s <= "1110";
wait for 2 ns;
s <= "1111";
wait for 2 ns;
end process;
end bhv_ALU_tb;
i know the mistake seems trivial "res isn't initialized" but I've been away from vhdl way too long and honestly dont know how to fix it, any ideas?
Firstly
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
Bad.. don't use. You don't even need them in this file.
If you ever need arithmentic, use numeric_std.
Then: the error is in the component ALU, becasue that should 'drive' res. But since you did not post the code of that, we cannot help you (yet).
p.s. currently you do not need to define a component in VHDL anymore. You could just write:
ALU_test: entity work.ALU port map
Related
I'm writing VHDL test bench for full adder
in Simulation i have tried this and getting the correct result
begin
A <= '0';
B <= '0';
C <= '0';
wait for 10 ns;
A <= '0';
B <= '0';
C <= '1';
wait for 10 ns;
A <= '0';
B <= '1';
C <= '0';
wait for 10 ns;
A <= '0';
B <= '1';
C <= '1';
wait for 10 ns;
A <= '1';
B <= '0';
C <= '0';
wait for 10 ns;
A <= '1';
B <= '0';
C <= '1';
wait for 10 ns;
A <= '1';
B <= '1';
C <= '0';
wait for 10 ns;
A <= '1';
B <= '1';
C <= '1';
wait for 10 ns;
wait;
end process;
but i don't want to write all this i just want to use for loop like in verilog
for i in 0 to 7 loop
{A,B,C} <= i;
wait for 10 ns;
end loop;
I Know assigning A, B, C to i is not right in VHDL?
how do we do that what are the correct syntax?
Yes you can - VHDL 2008 allows aggregate assignments.
use ieee.numeric_std_unsigned.all;
for i in 0 to 7 loop
(A,B,C) <= to_slv(i, 3);
wait for 10 ns;
end loop;
This work under VHDL93 with Vivado 2018.1:
loop1: for i in 0 to 7 loop
(a,b,c) <= std_logic_vector(to_unsigned(i,3));
wait for 10ns;
end loop;
You will not need the library use ieee.numeric_std_unsigned.all; (which I do not know)
But you will need the standard ieee library:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Here is the testbench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
entity test_tb is
end entity;
architecture Behavioral of test_tb is
signal clk : std_logic;
signal a : std_logic;
signal b : std_logic;
signal c : std_logic;
begin
clkpr : process
begin
clk <='1';
wait for 10ns;
clk <= '0';
wait for 10ns;
end process;
test_pr : process
begin
loop: for i in 0 to 7 loop
(a,b,c) <= std_logic_vector(to_unsigned(i,3));
wait for 10ns;
end loop;
wait;
end process;
end Behavioral;
You can try this :
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- To use integer and unsigned
...
signal stimuli : std_logic_vector(2 downto 0); -- Equivalent of A, B, C
...
inst_full_adder : full_adder
port map
(
i_a => stimuli(0),
i_b => stimuli(1),
i_carry => stimuli(2),
...
);
...
for i in 0 to 7 loop
stimuli <= std_logic_vector(to_unsigned(i,3)); -- Conversion of your integer in std_logic_vector (3 is the size of your vector)
wait for 10 ns;
end loop;
I need an help with my code. I wrote that code for a simple project and now when I try to test it the output are all U.
The code is for a door, when badge go to 1 you have 3 attempts to send the right password for open the door. When the badge go on 0 the door closes.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Porta is
Port ( Badge : in STD_LOGIC;
Comb : in STD_LOGIC_VECTOR(15 downto 0);
Lock : out STD_LOGIC);
end Porta;
architecture Behavioral of Porta is
signal pass: STD_LOGIC_VECTOR(15 downto 0) := "1001100110011001";
signal tent: unsigned(1 downto 0) := "00"; --Tent
signal l: STD_LOGIC := '0';
begin
p_badge: process(Badge)
begin
report "Process Badge!";
if Badge = '1' then
report "Process Badge dentro IF=1";
tent <= (others => '0');
else
l <= '0';
end if;
end process p_badge;
--Contatore tentativi e controllo combinazione
p_pass: process(Comb)
begin
report "Process Confirm!";
if tent /= "11" then
if Comb = pass then
report "Process Confirm, Comb=pass";
l <= '1';
tent <= (others => '0');
elsif Comb /= pass then
report "Process Confirm, Comb!=pass";
tent <= tent+"01";
end if;
else
report "tent=11";
end if;
end process p_pass;
--Processo per il lock
p_lock: process(l)
begin
report "Process LOCK!!";
if l = '1' then
Lock <= '1';
else
Lock <= '0';
end if;
end process p_lock;
end Behavioral;
EDIT: I simplify the code, but the value of Lock don't show in ISIM and an error occur many times: Instance /porta_tb4/uut/ : Warning: NUMERIC_STD."/=": metavalue detected, returning TRUE.
I post the simple test I create
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Porta_tb4 IS
END Porta_tb4;
ARCHITECTURE behavior OF Porta_tb4 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Porta
PORT(
Badge : IN std_logic;
Comb : IN std_logic_vector(15 downto 0);
Lock : OUT std_logic
);
END COMPONENT;
--Inputs
signal Badge : std_logic := '0';
signal Comb : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal Lock : std_logic;
BEGIN
uut: Porta PORT MAP (
Badge => Badge,
Comb => Comb,
Lock => Lock
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
Badge <= '1';
wait for 100 ns;
Comb <= "1001100110010011";
wait for 100 ns;
Comb <= "1001100110110011";
wait for 100 ns;
Comb <= "1001101110010011";
wait for 100 ns;
Comb <= "1011101110010011";
wait for 100 ns;
Badge <= '1';
wait for 100 ns;
Comb <= "1001100110011001";
wait for 100 ns;
Badge <= '0';
-- insert stimulus here
wait;
end process;
END;
Here is the code I have written for a 16 bit adder - The results of this files should be compared with a adder written in functional format: A+B, so they should make sense. The files are uploaded here:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Full_Adder_16 is
Port ( a : in STD_LOGIC_VECTOR (15 downto 0);
b : in STD_LOGIC_VECTOR (15 downto 0);
s : out STD_LOGIC_VECTOR (15 downto 0));
end Full_Adder_16;
architecture Behavioral of Full_Adder_16 is
component Full_Adder
port(x, y, cin: in std_logic;
sum, cout: out std_logic);
end component;
type cinout is array (0 to 15) of std_logic;
signal c : cinout;
signal cout : STD_LOGIC;
begin
c(0) <= '0';
adding: for i in 15 downto 0 generate
leftmost: if i=15 generate
Full_Adder_15: Full_Adder port map (x => a(i), y => b(i), cin => c(i), sum => s(i), cout => cout);
end generate;
otherwise: if i/=15 generate
Full_Adder_x: Full_Adder port map (x => a(i), y => b(i), cin => c(i), sum => s(i), cout => c(i+1));
end generate;
end generate;
end Behavioral;
And here is the testbench:
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
entity Full_Adder_16_tb is
end;
architecture bench of Full_Adder_16_tb is
component Full_Adder_16
Port ( a : in STD_LOGIC_VECTOR (15 downto 0);
b : in STD_LOGIC_VECTOR (15 downto 0);
s : out STD_LOGIC_VECTOR (15 downto 0));
end component;
signal a: STD_LOGIC_VECTOR (15 downto 0);
signal b: STD_LOGIC_VECTOR (15 downto 0);
signal s: STD_LOGIC_VECTOR (15 downto 0);
begin
uut: Full_Adder_16 port map ( a => a,
b => b,
s => s );
stimulus: process
begin
-- Put initialisation code here
A <= "0100010010110000";
B <= "0001010111011110";
wait for 10 ns;
A <= "0011000011110111";
B <= "0100000101000001";
wait for 10 ns;
A <= "0000000000000001";
B <= "0010011000000111";
wait for 10 ns;
A <= "0011110010110011";
B <= "1000111101011110";
wait for 10 ns;
A <= "0010000100100001";
B <= "1111101000100111";
wait for 10 ns;
A <= "0001011100100011";
B <= "0101101101101101";
wait for 10 ns;
A <= "1011000110111001";
B <= "1001011001011111";
wait for 10 ns;
A <= "0000001011001010";
B <= "1000011011101011";
wait for 10 ns;
A <= "0011110110100000";
B <= "1100111000000010";
wait for 10 ns;
A <= "0100000111111000";
B <= "0001001111100101";
wait for 10 ns;
A <= "1011111001111100";
B <= "0100001101010111";
wait for 10 ns;
A <= "1111000110000001";
B <= "1010000100001110";
wait for 10 ns;
A <= "0111000111001011";
B <= "1011000111010100";
wait for 10 ns;
A <= "1011011101101010";
B <= "1100111100101110";
wait for 10 ns;
A <= "1111001001010111";
B <= "0110010000100001";
wait for 10 ns;
A <= "0111111101101100";
B <= "0111000100001111";
wait for 10 ns;
A <= "0000111101111000";
B <= "1100011111101100";
wait for 10 ns;
A <= "0011100001100111";
B <= "1010101100100000";
wait for 10 ns;
A <= "1111111101000111";
B <= "0110111101011100";
wait for 10 ns;
A <= "0011111101000001";
B <= "1100100001100100";
wait for 10 ns;
A <= "1011011111000111";
B <= "1000111101011011";
wait for 10 ns;
A <= "1001011010010100";
B <= "0110001100101111";
wait for 10 ns;
A <= "1111111000100101";
B <= "1111111110001010";
wait for 10 ns;
A <= "1011100101000001";
B <= "0000100000000011";
-- Put test bench stimulus code here
wait;
end process;
end;
I just need the sum value since the result will be an alu output. But the result is wrong for some numbers, here is the wave form:
I have used the same adder to write a code for a multiplier but it works fine. Any comments to solve this problem will be appreciated.
The Full_adder is as follows:
library IEEE;
use IEEE.std_logic_1164.all;
entity Full_Adder is
port(x, y, cin: in std_logic;
sum, cout: out std_logic);
end Full_Adder;
architecture my_dataflow of Full_Adder is
begin
sum <= (x xor y) xor cin;
cout <= (x and y) or (x and cin) or (y and cin);
end my_dataflow;
In the Isim wave window my internal signals and outputs appear green and as initialized but all of my inputs appear as "UU" even though they are initialized as well. I am simply trying to add 1 whenever either of the two inputs are 1. The code synthesizes fine without warnings.
Any ideas?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity scoreboard2 is
Port ( clk : in STD_LOGIC;
T1 : in STD_LOGIC;
T2 : in STD_LOGIC;
Output : out STD_LOGIC_VECTOR (3 downto 0));
end scoreboard2;
architecture Behavioral of scoreboard2 is
signal output_temp: STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal score1,score2: unsigned(1 downto 0) := "00";
signal score3: unsigned(3 downto 0):= "0000";
begin
proc: process(T1,T2,clk)
begin
if(rising_edge(clk)) then
if(T1 = '1') then
score1 <= score1 + 1;
end if;
if(T2 = '1') then
score2 <= score2 + 1;
end if;
end if;
end process proc;
score3 <= score1 & score2;
output_temp <= STD_LOGIC_VECTOR(score3);
Output <= output_temp;
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY test6 IS
END test6;
ARCHITECTURE behavior OF test6 IS
COMPONENT scoreboard2
PORT(
clk : IN std_logic;
T1 : IN std_logic;
T2 : IN std_logic;
Output : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '1';
signal T1 : std_logic := '1';
signal T2 : std_logic := '1';
--Outputs
signal Output : std_logic_vector(3 downto 0) := "0000";
signal output_temp: STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal score1,score2: unsigned(1 downto 0) := "00";
signal score3: unsigned(3 downto 0):= "0000";
constant clk_period : time := 10 ns;
BEGIN
uut: scoreboard2 PORT MAP (
clk => clk,
T1 => T1,
T2 => T2,
Output => Output
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stim_proc: process
begin
wait for 100 ns;
T1 <= '1';
wait;
end process;
END;
I don't have Isim but some simulators allow you to run a top level design with a port having unconnected inputs. It's usually synonymous with the ability to do interactive simulation (run, stop, step, force inputs, etc.).
Chapter 5 of ise_tutorial_ug695.pdf, March 1, 2011 (v13.1) says you need a test bench, i don't have all the documentation to determine whether that is enforced or not.
For a test bench:
library ieee;
use ieee.std_logic_1164.all;
entity scoreboard_tb is
end entity;
architecture test of scoreboard_tb is
signal clk: std_logic := '0';
signal T1: std_logic := '0';
signal T2: std_logic := '0';
signal RESULT: std_logic_vector(3 downto 0);
begin
UNDER_TEST:
entity work.scoreboard2
port map (
clk => clk,
T1 => T1,
T2 => T2,
Output => RESULT
);
CLOCK:
process
begin
if Now > 340 ns then -- simulation stops with no signal events
wait;
end if;
clk <= not clk;
wait for 20 ns;
end process;
STIMULUS:
process
begin
wait for 40 ns;
T1 <= '1';
wait for 40 ns;
T2 <= '1';
wait for 40 ns;
T1 <= '0';
T2 <= '0';
wait for 40 ns;
T2 <= '1';
wait for 40 ns;
T2 <= '0';
T1 <= '1';
wait for 40 ns;
T1 <= '0';
wait;
end process;
end architecture;
ghdl produces:
for you're scoreboard2 entity/architecture pair analyzed unchanged.
I don't have Isim either. Probably the softwave itself didn't work well. If there is a wave editor or something similar in Isim, use it instead of a testbench. Then simulate your project again. Hope this helps:)
-----------begin part1.vhdl---------------------
library ieee;
use ieee.std_logic_1164.all;
entity part1 is
generic ( width : integer :=7);
PORT( a, b, c, d: IN std_logic_vector(width downto 0);
sel: IN std_logic_vector(1 downto 0);
result: OUT std_logic_vector(width downto 0)
);
end part1;
architecture muxbehav of part1 is
BEGIN
result <= a after 5 ns when sel="00" else
b after 5 ns when sel="01" else
c after 5 ns when sel="10" else
d after 5 ns;
end muxbehav;
-----------end part1.vhdl---------------------
-----------begin part1_tb.vhdl------------------
library ieee;
use ieee.std_logic_1164.all;
entity part1_tb is
generic( width : integer := 7);
end part1_tb;
architecture tb of part1_tb is
signal t_a: std_logic_vector(width downto 0):="00000000";
signal t_b: std_logic_vector(width downto 0):="00000000";
signal t_c: std_logic_vector(width downto 0):="00000000";
signal t_d: std_logic_vector(width downto 0):="00000000";
signal t_s: std_logic_vector(1 downto 0);
signal t_o: std_logic_vector(width downto 0);
component part1
generic(width : integer);
PORT( a, b, c, d: IN std_logic_vector(width downto 0);
sel: IN std_logic_vector(1 downto 0);
result: OUT std_logic_vector(width downto 0)
);
end component;
begin
U_part1: part1 generic map(width) port map(a=>t_a, b=>t_b, c=>t_c, d=>t_d, sel=>t_s, result=>t_o);
process
begin
t_a <= "11111111";
t_b <= "00000001";
t_c <= "10101010";
t_d <= "01010101";
wait for 10 ns;
t_s <= "00";
wait for 6 ns;
assert (t_o="11111111") report "Error input a" severity error;
wait for 10 ns;
t_s <= "01";
wait for 6 ns;
assert (t_o="00000001") report "Error input b" severity error;
wait for 10 ns;
t_s <= "10";
wait for 6 ns;
assert (t_o="10101010") report "Error input c" severity error;
wait for 10 ns;
t_s <= "11";
wait for 6 ns;
assert (t_o="01010101") report "Error input d" severity error;
wait;
end process;
end tb;
-----------end part1_tb.vhdl------------------
Hello, this is my first code I've written in VHDL. It's a simple 4 to 1 MUX that can take in a vector of any width. However, when I try running my testbench, GHDL just hangs. I've looked at testbenches similar to mine, but I still cannot find why mine is hanging. Any ideas?
Hmmm. I can't see any reason for it to hang.
I just tried your code in ghdl0.29 on Ubuntu 10.04 - works fine for me (in that it exits without printing any messages, so it seems your code works :) The waves look convincing in gtkwave also.
Can you try deleting your work folder and the executable and recompile?
Sorry, that's not really an answer that gets you forward!