VHDL coding in Isim Wave Window - vhdl

Question

In the Isim wave window my internal signals and outputs appear green and as initialized but all of my inputs appear as "UU" even though they are initialized as well. I am simply trying to add 1 whenever either of the two inputs are 1. The code synthesizes fine without warnings.
Any ideas?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity scoreboard2 is
Port ( clk : in STD_LOGIC;
T1 : in STD_LOGIC;
T2 : in STD_LOGIC;
Output : out STD_LOGIC_VECTOR (3 downto 0));
end scoreboard2;
architecture Behavioral of scoreboard2 is
signal output_temp: STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal score1,score2: unsigned(1 downto 0) := "00";
signal score3: unsigned(3 downto 0):= "0000";
begin
proc: process(T1,T2,clk)
begin
if(rising_edge(clk)) then
if(T1 = '1') then
score1 <= score1 + 1;
end if;
if(T2 = '1') then
score2 <= score2 + 1;
end if;
end if;
end process proc;
score3 <= score1 & score2;
output_temp <= STD_LOGIC_VECTOR(score3);
Output <= output_temp;
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY test6 IS
END test6;
ARCHITECTURE behavior OF test6 IS
COMPONENT scoreboard2
PORT(
clk : IN std_logic;
T1 : IN std_logic;
T2 : IN std_logic;
Output : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '1';
signal T1 : std_logic := '1';
signal T2 : std_logic := '1';
--Outputs
signal Output : std_logic_vector(3 downto 0) := "0000";
signal output_temp: STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal score1,score2: unsigned(1 downto 0) := "00";
signal score3: unsigned(3 downto 0):= "0000";
constant clk_period : time := 10 ns;
BEGIN
uut: scoreboard2 PORT MAP (
clk => clk,
T1 => T1,
T2 => T2,
Output => Output
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stim_proc: process
begin
wait for 100 ns;
T1 <= '1';
wait;
end process;
END;

Answer 1

I don't have Isim but some simulators allow you to run a top level design with a port having unconnected inputs. It's usually synonymous with the ability to do interactive simulation (run, stop, step, force inputs, etc.).
Chapter 5 of ise_tutorial_ug695.pdf, March 1, 2011 (v13.1) says you need a test bench, i don't have all the documentation to determine whether that is enforced or not.
For a test bench:
library ieee;
use ieee.std_logic_1164.all;
entity scoreboard_tb is
end entity;
architecture test of scoreboard_tb is
signal clk: std_logic := '0';
signal T1: std_logic := '0';
signal T2: std_logic := '0';
signal RESULT: std_logic_vector(3 downto 0);
begin
UNDER_TEST:
entity work.scoreboard2
port map (
clk => clk,
T1 => T1,
T2 => T2,
Output => RESULT
);
CLOCK:
process
begin
if Now > 340 ns then -- simulation stops with no signal events
wait;
end if;
clk <= not clk;
wait for 20 ns;
end process;
STIMULUS:
process
begin
wait for 40 ns;
T1 <= '1';
wait for 40 ns;
T2 <= '1';
wait for 40 ns;
T1 <= '0';
T2 <= '0';
wait for 40 ns;
T2 <= '1';
wait for 40 ns;
T2 <= '0';
T1 <= '1';
wait for 40 ns;
T1 <= '0';
wait;
end process;
end architecture;
ghdl produces:
for you're scoreboard2 entity/architecture pair analyzed unchanged.

Answer 2

I don't have Isim either. Probably the softwave itself didn't work well. If there is a wave editor or something similar in Isim, use it instead of a testbench. Then simulate your project again. Hope this helps:)