How to fix 'U' output in VHDL - vhdl

Question

I need an help with my code. I wrote that code for a simple project and now when I try to test it the output are all U.
The code is for a door, when badge go to 1 you have 3 attempts to send the right password for open the door. When the badge go on 0 the door closes.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Porta is
Port ( Badge : in STD_LOGIC;
Comb : in STD_LOGIC_VECTOR(15 downto 0);
Lock : out STD_LOGIC);
end Porta;
architecture Behavioral of Porta is
signal pass: STD_LOGIC_VECTOR(15 downto 0) := "1001100110011001";
signal tent: unsigned(1 downto 0) := "00"; --Tent
signal l: STD_LOGIC := '0';
begin
p_badge: process(Badge)
begin
report "Process Badge!";
if Badge = '1' then
report "Process Badge dentro IF=1";
tent <= (others => '0');
else
l <= '0';
end if;
end process p_badge;
--Contatore tentativi e controllo combinazione
p_pass: process(Comb)
begin
report "Process Confirm!";
if tent /= "11" then
if Comb = pass then
report "Process Confirm, Comb=pass";
l <= '1';
tent <= (others => '0');
elsif Comb /= pass then
report "Process Confirm, Comb!=pass";
tent <= tent+"01";
end if;
else
report "tent=11";
end if;
end process p_pass;
--Processo per il lock
p_lock: process(l)
begin
report "Process LOCK!!";
if l = '1' then
Lock <= '1';
else
Lock <= '0';
end if;
end process p_lock;
end Behavioral;
EDIT: I simplify the code, but the value of Lock don't show in ISIM and an error occur many times: Instance /porta_tb4/uut/ : Warning: NUMERIC_STD."/=": metavalue detected, returning TRUE.
I post the simple test I create
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Porta_tb4 IS
END Porta_tb4;
ARCHITECTURE behavior OF Porta_tb4 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Porta
PORT(
Badge : IN std_logic;
Comb : IN std_logic_vector(15 downto 0);
Lock : OUT std_logic
);
END COMPONENT;
--Inputs
signal Badge : std_logic := '0';
signal Comb : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal Lock : std_logic;
BEGIN
uut: Porta PORT MAP (
Badge => Badge,
Comb => Comb,
Lock => Lock
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
Badge <= '1';
wait for 100 ns;
Comb <= "1001100110010011";
wait for 100 ns;
Comb <= "1001100110110011";
wait for 100 ns;
Comb <= "1001101110010011";
wait for 100 ns;
Comb <= "1011101110010011";
wait for 100 ns;
Badge <= '1';
wait for 100 ns;
Comb <= "1001100110011001";
wait for 100 ns;
Badge <= '0';
-- insert stimulus here
wait;
end process;
END;