3-bit serial input bubble sort in VHDL not sorting - sorting

Question

I am trying to design a 3-bit serial input bubble sort and have not been able to get the output to actually sort.
Unfortunately, I am not very familiar with VHDL, or programming in general.
I have read that a potential problem of mine is the way I am using signals and assigning them within my process. However, when I tried correcting that and got it to compile, my output was broken.
There was another question about bubble sort in VHDL using arrays that I also tried to base mine off of, but was also unsuccessful. The main thing I tried from that was the for i in ___ to ___ loop process.
Below is my code and test bench that I have most recently been using.
Any advice or explanations would be greatly appreciated!
library ieee;
use ieee.std_logic_1164.all;
entity bubble_sort_bs is
generic (
width : integer := 3);
port (
X0, X1, X2 : in std_logic;
Y0, Y1, Y2 : out std_logic;
clk, enable : in std_logic);
end entity bubble_sort_bs;
architecture bubble_sort_bs_behav of bubble_sort_bs is
signal comb_out : std_logic;
signal inp : std_logic_vector((width-1) downto 0);
signal inp1 : std_logic_vector((width-1) downto 0);
signal inp2 : std_logic_vector((width-1) downto 0);
signal pass_in, pass_out : std_logic_vector((width-1) downto 0);
signal outp : std_logic_vector((width-1) downto 0); --trash
signal x_vector : std_logic_vector((width-1) downto 0);
begin
x_vector <= X0 & X1 & X2;
Y0 <= pass_out(2);
Y1 <= pass_out(1);
Y2 <= pass_out(0);
Output : process(all)
begin
if rising_edge(clk) then
if enable <= '1' then
inp1 <= x_vector;
inp2 <= pass_in;
end if;
end if;
if inp1 > inp2 then --x_vector
comb_out <= '1';
outp <= inp1;
pass_in <= inp2;
elsif inp2 > inp1 then --x_vector
comb_out <= '0';
outp <= inp2;
pass_in <= inp1;
----inp2 <= inp1;
elsif inp2 = inp1 then
comb_out <= '0';
outp <= inp2;
pass_in <= inp1;
end if;
pass_out <= outp;
end process Output;
end architecture bubble_sort_bs_behav;
Testbench:
library ieee;
use ieee.std_logic_1164.all;
entity bubble_sort_bs_tb is
end entity bubble_sort_bs_tb;
architecture tb_behav of bubble_sort_bs_tb is
component bubble_sort_bs
generic (
width : integer);
port (
X0, X1, X2 : in std_logic;
Y0, Y1, Y2 : out std_logic;
clk, enable : std_logic
);
end component;
constant bit_width : integer := 3;
signal inp, outp : std_logic_vector((bit_width-1) downto 0);
signal t_clk, t_enable : std_logic := '0';
begin
U1 : bubble_sort_bs
generic map (bit_width)
port map (
X0 => inp(0),
X1 => inp(1),
X2 => inp(2),
Y0 => outp(0),
Y1 => outp(1),
Y2 => outp(2),
clk => t_clk,
enable => t_enable
);
t_clk <= not t_clk after 5 ns;
test_process : process
begin
inp <= "001";
t_enable <= '1';
wait for 20 ns;
inp <= "100";
t_enable <= '1';
wait for 20 ns;
inp <= "111";
t_enable <= '1';
wait for 20 ns;
inp <= "000";
t_enable <= '1';
wait for 20 ns;
wait;
end process;
end tb_behav;

Answer 1

Okay there are multiple things wrong with your code.
First of all your mapping from input to x_vector has the bits reversed, which you also do at your output.
Next pass_in will never get a value, resulting in that your first comparison inp1 > inp2 always is true. So what your actually doing is giving an input signal comparing it with nothing and then returning it a clock cycle later. See Picture.
To do a bubble sort you at least need to have two inputs in the beginning.
As said by others try some tutorials to get more familiar with VHDL before continuing. I can recommend the asic-world tutorial.
Good luck!