VHDL Getting a simulation fatal error in the loading design in modelsim - vhdl

Question

(Yes I know there's an easier way, yes my professor is asking for the long way.)
The following is the code for my 1 bit adder/subtractor.
library ieee;
use ieee.std_logic_1164.all;
entity FA1Bit is
port(x,y,Cin: in std_logic;
op: in std_logic;
S, Cout: out std_logic);
end FA1Bit;
architecture FA1Bit_arch of FA1Bit is
begin
behavior : PROCESS(op,x,y,Cin)
begin
if op = '0' then --if we're adding the bits;
if Cin = '0' then
if x = y then
S <= '0';
if (x= '1' and y = '1') then
Cout <= '1';
else --if x = 0 and y = 0;
Cout <= '0';
end if;
else --if x not equal to y;
S <= '1';
Cout <= '0';
end if;
else --if Cin = 1 then;
if x = y then
S <= '1';
if (x= '1' and y = '1') then
Cout <= '1';
else --if x = 0 and y = 0;
Cout <= '0';
end if;
else --if x not equal to y;
S <= '0';
Cout <= '1';
end if;
end if;
else -- if we're subtracting bits (op = 1);
if Cin = '0' then
if x = y then
Cout <= '0';
S <= '0';
elsif (x ='1' and y = '0') then
Cout <= '0';
S <= '1';
else --if x not equal to y;
S <= '1';
Cout <= '1';
end if;
else --if Cin = 1 then;
if x = y then
Cout <= '1';
S <= '1';
elsif (x ='1' and y = '0') then
Cout <= '0';
S <= '0';
else --if x not equal to y;
S <= '0';
Cout <= '1';
end if;
end if;
end if;
end PROCESS;
end FA1Bit_arch;
Now I use this component in my 4 bit adder/subtractor in this code:
library IEEE;
use IEEE.std_logic_1164.all;
entity FA4Bit is
port (
X : in STD_LOGIC_VECTOR(3 downto 0);
Y : in STD_LOGIC_VECTOR(3 downto 0);
C0: in STD_LOGIC;
S : out STD_LOGIC_VECTOR(3 downto 0);
C4: out STD_LOGIC;
OP1: in STD_LOGIC_VECTOR(3 DOWNTO 0));
end FA4Bit;
architecture FA4Bit_arch of FA4Bit is
component FA1bit
port ( X: in STD_LOGIC; Y: in STD_LOGIC; CIN : in STD_LOGIC;
SI : out STD_LOGIC; COUT: out STD_LOGIC;
OPA : in STD_LOGIC);
end component;
signal C : std_logic_vector(1 to 3);
begin
U1: FA1bit port map (X=>X(0), Y=>Y(0), CIN=> C0, SI=>S(0), COUT=>C(1), OPA => OP1(0));
U2: FA1bit port map (X=>X(1), Y=>Y(1), CIN=> C(1), SI=>S(1), COUT=>C(2), OPA => OP1(1));
U3: FA1bit port map (X=>X(2), Y=>Y(2), CIN=> C(2), SI=>S(2), COUT=>C(3), OPA => OP1(2));
U4: FA1bit port map (X=>X(3), Y=>Y(3), CIN=> C(3), SI=>S(3), COUT=>C4, OPA => OP1(3));
end FA4Bit_arch;
Everything compiles perfectly same goes for the following testbench.
library ieee;
use ieee.std_logic_1164.all;
entity FA4Bit_tb is
end ;
architecture arch of FA4Bit_tb is
component FA4Bit
port ( X1 : in std_logic_vector(3 downto 0);
Y : in std_logic_vector(3 downto 0);
C0 : in std_logic;
S : out std_logic_vector(3 downto 0);
C4 : out std_logic;
OP1: in std_logic_vector(3 downto 0));
end component;
signal X : std_logic_vector(3 downto 0) := "0000";
signal Y : std_logic_vector(3 downto 0) := "0000";
signal C0 : std_logic := '0';
signal opa: std_logic_vector(3 downto 0) := (others=>'0');
signal S : std_logic_vector(3 downto 0);
signal C4 : std_logic;
begin
UUT : FA4Bit
port map (X1 => X, Y => Y, C0 => C0, S => S, C4 => C4, OP1=> opa);
X <= not X after 5 ns;
Y <= not Y after 7 ns;
opa <= not opa after 9 ns;
end arch;
However, I'm receiving a FATAL ERROR in the loading design.
# ** Fatal: (vsim-3817) Port "X" of entity "fa4bit" is not in the component being instantiated.
# Time: 0 ns Iteration: 0 Instance: /fa4bit_tb/UUT File: C:/Users/Omar/Desktop/320 PROJECT 3ANJAD HAL MARRA/FA4Bit.vhd Line: 5
# FATAL ERROR while loading design
# Error loading design

Answer 1

This is one reason why I hate component instantiations. In your component instantiation, the port is called X1, not X. Renaming to X should fix this issue. Then you have a couple of similar ones to fix (OP and S on FA1bit).
If you use entity instantiations, then a lot of problems like this go away.