I am working on designing a mandelbrot viewer and I am designing hardware for squaring values. My squarer is recursively built where a 4bit squarer relies on 2, 2bit squarers. so for my 16 bit squarer, that has 2 8bits squarers, and each one of those has 2 4bit squarer's.
As you can see the recursivity begins to make the design blow up in complexity. To help speed up my design i would like to use a 4input ROM that emulates a 4bit squarer. So when you enter 3 in the rom, it outputs 9, when you enter 15, it outputs 225.
I know that a normal LUT implemented in a logic cell ay have 3 or 4 input variables and only 1 output, but i need an 8 bit output so I need more of a ROM then a LUT.
Any and all help is appreciated, Im curious how the FPGA will store those ROMs and if storing it in ROM would be faster than computing the 4input Square.
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Jarvi
To square a 4-bit number explicitly using LUTs, you would need to use 8 4-input LUTs. Each LUT's output would give you one bit of the 8-bit product.
The overall size and fmax performance of your design may be achieved with this approach, using larger block RAM primitives (as ROM), dedicated MAC (multiply-accumulate) units, or by using the normal mulitiplication operator * and relying on your synthesis tool's optimization.
You may also want to review some research papers related to this topic, for example here.
I am currently working on a school project and one of my tasks is to implement a 16-bit by 16-bit 2's complement integer divider as a digital logic circuit (in other words 16-bit input divided by another 16-bit input). The output is straight forward where it shows quotient Q and remainder R. Also special cases like dividing by zero are taken care of with preset conditions.
My primary issue here is that the only way that I am able to implement this is by using long division or a very long recurring subtraction. Even then, I'm not sure how to implement long division without creating a messy circuit. Open to suggestions in case there is no other way.
Because of this, I have looked into other division algorithms like the Newton-Raphson division, but I don't think those algorithms are possible to implement as a logic circuit (and I just don't know and understand how too..). So I was wondering if there were any speed-friendly division algorithms to do this.
I am trying to create a half adder circuit using logisim to compute two 4 bit binary numbers but somehow Logisim tells me that I have incompatible widths and I therefore have to change the bit width of every single component including the carry-out which is suppose to be a 1 bit (showing carry 1 or carry 0). Now I understand that my output has to be at least 4 bit in length and I need an extra bit as a carry out but even when I change the length the way Logisim wants then my design does not work anymore.
Half adder of a 2 four bit binaries
It's simply because the input width on the AND gate is 1 bit. You can't have a 4-bit output going into a 1-bit input.
a real junior question with hopefully a junior answer, regarding one of the main assignments of VHDL (concurrent selective assignment) can anyone explain what a VHDL compiler would synthesise the following description into?
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Q2 IS
PORT (a,b,c,d : IN std_logic;
EW_NS : OUT std_logic
);
END ENTITY Q2;
ARCHITECTURE hybrid OF Q2 IS
SIGNAL INPUT : std_logic_vector(3 DOWNTO 0);
SIGNAL EW_NS : std_logic;
BEGIN
INPUT <= (a & b & c & d); -- concatination
WITH (INPUT) SELECT
EW_NS <= '1' WHEN "0001"|"0010"|"0011"|"0110"|"1011",
'0' WHEN OTHERS;
END ARCHITECTURE hybrid;
Why do I ask? well I have previously gone about things the wrong way i.e. describing things on VHDL before making a block diagram of the components needed. I would envisage this been synthed as a group of and gate logic ?
Any help would be really helpful.
Thanks D
You need to look at the user guide for your target FPGA, and understand what is contained within one 'logic element' ('slice' in Xilinx terminology). In general an FPGA does not implement combinatorial logic by connecting up discrete gates like AND, OR, etc. Instead, a logic element will contain one or more 'look-up tables', with typically four (but now 6 in some newer devices) inputs. The inputs to this look up table (LUT) are the inputs to your logic function, and the output is one of the outputs of the function. The LUT is then programmed as a ROM, allowing your input signals to function as an address. There is one ROM entry for every possible combination of inputs, with the result being the intended logic function.
A function with several outputs would simply use several of these LUTs in parallel, with the same inputs, one LUT for each of the function's outputs. A function requiring more inputs than the LUT has (say, 7 inputs, where a LUT has only 4), simply combines two LUTs in parallel, using a multiplexer to choose between the output of the two LUTs. This final multiplexer uses one of the input signals as it's control, and again every possible combination of inputs is accounted for.
This may sound inefficient for creating something simple like an AND gate, but the benefit is that this simple building block (a LUT) can implement absolutely any combinatorial function. It's also worth noting that an FPGA tool chain is extremely good at optimising logic functions in order to simplify them, and to better map them into the FPGA. The LUT provides a highly generic element for these tools to target.
A logic element will also contain some dedicated resources for functions that aren't well suited to the LUT approach. These might include dedicated carry chains for adders, multiplexers for combining the output of several LUTS, registers (most designs are synchronous). LUTs can also sometimes be configured as small shift registers or RAM elements. External to the logic elements, there will be more specific blocks like large multipliers, larger memories, PLLs, etc, none of which can be as efficiently implemented using LUT resource. Again, this will all be explained in the user guide for your target FPGA.
Back in the day, your code would have been implemented as a single 74150 TTL circuit, which is a 16-to-1 mux. you have a 4-bit select (INPUT), and this selects one of 16 inputs to the chip, which is routed to a single output ('EW_NS`). The 74150 is obsolete and I can't find any datasheets, but it's easy to find diagrams of what an 8-to-1 mux looks like (here, for example). The 16->1 is identical, but everything is wider. My old TI databook shows basically exactly the diagram at this link doubled up.
But - wait. Your problem is easier, because you're not routing real inputs to the output - you're just setting fixed data values. On the '150, you do this by wiring 5 of the 16 inputs to 1, and the remaining 11 to 0. This makes the logic much easier.
The 74150 has basiscally exactly the same functionality as a 4-input look-up table (where the fixed look-up data is the same as fixed levels at the '150 inputs), so it's trivial to implement your entire circuit in a single LUT in an FPGA, as per scary_jeff's answer, rather than using a NAND-level implementation. In a proper chip, though, it would be implemented as a sum-of-products, or something similar (exactly what's in the linked diagram). In this case, draw a K-map and find a minimum solution. My 2 minutes on the back of an envelope comes up with three 3-input AND gates, driving a 3-input OR gate. I'll leave it as an exercise to you to check this :)
I'm working on a circuit which performs basic operations such as addition and subtraction using logic gates.
Right now, it takes 3 inputs, two 4 bit numbers, and a 3 bit opcode which indicates what operation to perform.
It seems that a 3-8 decoder would be a good idea here. This is my mockup!
To give a little more context, here is what my adder circuit looks like (+). I designed it to take two 4 bit numbers X & Y:
However, what I am confused about is the fact that I have to feed in 4 inputs or 4 wires to each of the circuit that handles it's respective operations (+, -, =, etc). It appears to only connect one wire to the circuit I need to get to. I need to actually connect 8 wires, as I have to feed in the to 4 bit numbers.
UPDATE: I ended up using a MUX to select the output that I want.
An adder doesn't need an input to tell it to add, because that's all it does.
A 4-bit full adder should have
4 input signals for each operand, total 8
A carry-in input signal if you are also using it for subtraction
5 output signals, the high-order one may be used to generate an overflow flag
Your decoder is a separate component from all the function generators. You could put a tristate buffer on each function generator to connect them to a common data bus, and then the decoder would generate the tristate enable signals. Otherwise, you probably don't need a decoder, but you might look at a multiplexer (mux) instead.